From patchwork Thu Oct 19 13:26:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13429169 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9BB57CDB482 for ; Thu, 19 Oct 2023 13:28:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtT3i-0003ca-8I; Thu, 19 Oct 2023 09:27:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtT3d-0003aM-2a for qemu-devel@nongnu.org; Thu, 19 Oct 2023 09:27:25 -0400 Received: from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtT3a-0006Xl-5g for qemu-devel@nongnu.org; Thu, 19 Oct 2023 09:27:24 -0400 Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-1e19cb7829bso4903976fac.1 for ; Thu, 19 Oct 2023 06:27:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697722039; x=1698326839; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=7kNBu2eX1X8AHgLmoRKI6DQsuRe/7tTX2acgsC1oaaY=; b=Fhc5TNDD5fnrf3eLVM+yRnrkXS3XFzV92/itNZ96h9zRvvGl4DBQD6XoUIeDDMCcG3 Pgxyl0kY5PuppQI8BPx7P+sXiinalNNF9VkdR0Uy5aHNySzOo+zfvY7S2VtDGMk3Jktz 2MwxAExgv9oBNg4eI6xsO3BK3tcY8NTONd+phk5QRczU01qOmZox3wA29d2U0GoxQXzz r956/FeDyYJpcIFd9PghJIQl7tp/4w7c4rCNBoesq7A9WKxJO0ITe9CtJoyCTuxP/MeK 5aQlDXCe5+JnI2jueHf2iCjk6PohV8WpqY71TLNtzzXK5WLxm7c9Yj/6OQWjKvD44B4n 5euQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697722039; x=1698326839; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7kNBu2eX1X8AHgLmoRKI6DQsuRe/7tTX2acgsC1oaaY=; b=EmszxGgW59QbXkb0ypUMr5EFt063vR+nKOyIApPMZ5MUyDeS+7nQwWPOKN/BK46GEF GV9nDlNYYDQwQr4UXj3jmv/83Rm1Io+PZuN4zVy53+3tEdU5xzM9T324WBbG1Tnlnz07 gUR9yy4yGHPsI/QjCC3nM2MFF5GPRPfKY6nr1jARQqpvTyf110mUONmSrknLJdLg7ZM0 EbsXzHPaeMeHAj7smFD0SHhzH1sJycuqMccoLRafItEX+nbPkM9Dwctkpoh4dcCxel4s YlY79qM7mUmBbxkZiAAVGJBV9jQae5cL77LnzUImpJyUBiaUD6p0n6E+ZIeraUVRjB9N IAEw== X-Gm-Message-State: AOJu0Yw2I2ElBgVW5NwFtFh4enDqQ1e4MBhb0UrqtTrEzCtk0U49T6vQ xqoSpsfvOCC1Mv9Jv8dqyPpqBw== X-Google-Smtp-Source: AGHT+IHHNC9hxQYG8ab4n1xxGOfY75HExSt6ZNr0rK8uFsJ20M79FNhDPPhUi20ayvbnSfBKGCpWJQ== X-Received: by 2002:a05:6870:c14f:b0:1ea:2506:3e90 with SMTP id g15-20020a056870c14f00b001ea25063e90mr2093805oad.35.1697722039440; Thu, 19 Oct 2023 06:27:19 -0700 (PDT) Received: from sunil-laptop.dc1.ventanamicro.com ([2409:4071:6e8b:3a98:dd76:4e82:7da6:44ab]) by smtp.gmail.com with ESMTPSA id f11-20020a056a00228b00b0068feb378b89sm5273113pfe.171.2023.10.19.06.27.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:27:18 -0700 (PDT) From: Sunil V L To: qemu-riscv@nongnu.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Shannon Zhao , Peter Maydell , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [PATCH v3 00/12] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Date: Thu, 19 Oct 2023 18:56:36 +0530 Message-Id: <20231019132648.23703-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=sunilvl@ventanamicro.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series primarily enables external interrupt controllers (AIA and PLIC) in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and MMU related information. Below ECRs for these changes are approved by ASWG and will be available in next ACPI spec release. 1) MADT (AIA) - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing 2) RHCT - https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view?usp=sharing First two patches in this series are to migrate a couple of functions from ARM architecture to common code so that RISC-V doesn't need to duplicate the same. The patch set is based on Alistair's riscv-to-apply.next branch. These changes are also available in riscv_acpi_b2_v3 branch at: https://github.com/vlsunil/qemu/ Changes since v2: 1) Rebased to latest riscv-to-apply.next branch which needed changing ext_icboz to ext_zicboz in CMO patch. 2) Fixed node type in MMU node. 3) Added latest tags. Changes since v1: 1) As per Igor's suggestion, migrated fw_cfg and virtio creation functions to device specific file instead of generic aml-build.c. Since ACPI is optional, new files are created and enabled for build only when CONFIG_ACPI is enabled. 2) As per Igor's suggestion, properties are added to the GPEX PCI host to indicate MMIO ranges. The platform fw can initialize these to appropriate values and the DSDT generator can fetch the information from the host bus itself. This makes the code generic instead of machine specific. 3) Added PLIC patch from Haibo. 4) Rebased to latest riscv-to-apply.next and added RB tags as appropriate. Sunil V L (12): hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location hw/arm/virt-acpi-build.c: Migrate virtio creation to common location hw/riscv: virt: Make few IMSIC macros and functions public hw/riscv/virt-acpi-build.c: Add AIA support in RINTC hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT hw/riscv/virt-acpi-build.c: Add APLIC in the MADT hw/riscv/virt-acpi-build.c: Add CMO information in RHCT hw/riscv/virt-acpi-build.c: Add MMU node in RHCT hw/pci-host/gpex: Define properties for MMIO ranges hw/riscv/virt: Update GPEX MMIO related properties hw/riscv/virt-acpi-build.c: Add IO controllers and devices hw/riscv/virt-acpi-build.c: Add PLIC in MADT hw/arm/virt-acpi-build.c | 48 +---- hw/nvram/fw_cfg-acpi.c | 17 ++ hw/nvram/meson.build | 1 + hw/pci-host/gpex-acpi.c | 13 ++ hw/pci-host/gpex.c | 12 ++ hw/riscv/Kconfig | 1 + hw/riscv/virt-acpi-build.c | 342 +++++++++++++++++++++++++++++--- hw/riscv/virt.c | 72 +++---- hw/virtio/meson.build | 1 + hw/virtio/virtio-acpi.c | 28 +++ include/hw/nvram/fw_cfg_acpi.h | 9 + include/hw/pci-host/gpex.h | 28 ++- include/hw/riscv/virt.h | 26 +++ include/hw/virtio/virtio-acpi.h | 11 + 14 files changed, 492 insertions(+), 117 deletions(-) create mode 100644 hw/nvram/fw_cfg-acpi.c create mode 100644 hw/virtio/virtio-acpi.c create mode 100644 include/hw/nvram/fw_cfg_acpi.h create mode 100644 include/hw/virtio/virtio-acpi.h