From patchwork Wed Oct 25 20:07:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13436663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 597C6C25B6E for ; Wed, 25 Oct 2023 20:08:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvkAP-0007Ip-NZ; Wed, 25 Oct 2023 16:07:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvkAN-0007HW-LU for qemu-devel@nongnu.org; Wed, 25 Oct 2023 16:07:47 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvkA1-0003OE-KJ for qemu-devel@nongnu.org; Wed, 25 Oct 2023 16:07:47 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6bee11456baso120548b3a.1 for ; Wed, 25 Oct 2023 13:07:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698264443; x=1698869243; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Dd+lZHbJZ63yLPKpGaxGttWwXd+npdtCriCkwxmelvI=; b=F5Zxu0YDNKXwFLL3ijAg5+EyyE7Hf105EyNr2cN/F4GfhsgZJZ3U8D6Z/xEQIPzNK8 0kUanPt2Kt6d89mJvnf/BJF44FnHS6fJuzXjmVQ5lL7sTqsbXZ4KRQmL6ev35ubVS5ni RmsGN7Ag5JX4GS1nhIziZTG1f439mhfdk20NTEnSAUpzAWyCJmuz3pPuslcReJAahRTV n2AYnduGxVRtwjSO60vkZkjA0aG5mSrPURDuz8vwM9JFYCwGhZcVFd5SrXwturpKE32y 73T4tC5jpMb03cRJXHqjy7rWez9sQunTfR7rY3xsuPiiKwetKhJiEej5cgB5EF4MU1LK tv4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698264443; x=1698869243; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Dd+lZHbJZ63yLPKpGaxGttWwXd+npdtCriCkwxmelvI=; b=jFWW1lZzqMYyHEt2VEH5Lm++Z3ty2jOzVfTdTzzz7+bT8wrN/wJ26aJiXTDAelR0RM Oul+Lme4B3Hny+JcpUMyv12rXaViQFwEQ5+dLgNI59QV2WHDv0+SjbkQywNvnGP8LyOF 5wPx51OEW+tcwPmyu85ci82XBjUmOhVipEoVY0CevvY2LlrWUZFpvXSkJRn2jN4vN5qE C41EumxzT99qGr7uht2FKUJ65Jlr6IKpHhsUDT3rWWQbJinGU7Yp7qqXphBzRt5Uqh+n U27Xb1/osKbsEj1k8pro7VQv6IdDvHFuArWNacCPISUfLB2f9B2WXgNXC96Q9Q3YrLC6 /I9g== X-Gm-Message-State: AOJu0Yw8wsQFmVTKOSNnLhBbqtC9uwFyV7YpcH021oPLPY+bIf8MgXfP xdkt60Luahpm/OskAlxfvz9G6w== X-Google-Smtp-Source: AGHT+IFqvBI43Bj+m/OQPQ0tE97qp60WI1c/CKcdT87mPy6GgxB513E3Ibq6g8poZGD6N+0cRvWy4A== X-Received: by 2002:a05:6a00:1a09:b0:691:21:d9b9 with SMTP id g9-20020a056a001a0900b006910021d9b9mr13243389pfv.30.1698264442517; Wed, 25 Oct 2023 13:07:22 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id f1-20020aa79681000000b0068fe7c4148fsm9696768pfk.57.2023.10.25.13.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 13:07:21 -0700 (PDT) From: Sunil V L To: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Peter Maydell , Shannon Zhao , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Gerd Hoffmann , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [PATCH v4 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Date: Thu, 26 Oct 2023 01:37:00 +0530 Message-Id: <20231025200713.580814-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=sunilvl@ventanamicro.com; helo=mail-pf1-x436.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series primarily enables external interrupt controllers (AIA and PLIC) in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and MMU related information. Below ECRs for these changes are approved by ASWG and will be available in next ACPI spec release. 1) MADT (AIA) - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing 2) RHCT - https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view?usp=sharing First two patches in this series are to migrate a couple of functions from ARM architecture to common code so that RISC-V doesn't need to duplicate the same. The patch set is based on Alistair's riscv-to-apply.next branch. These changes are also available in riscv_acpi_b2_v4 branch at: https://github.com/vlsunil/qemu/ Changes since v3: 1) Addressed comments from Daniel and Drew. 2) Added a new patch in microvm to use common function for virtio in DSDT. 3) Rebased to latest riscv-to-apply.next branch and added tags. Changes since v2: 1) Rebased to latest riscv-to-apply.next branch which needed changing ext_icboz to ext_zicboz in CMO patch. 2) Fixed node type in MMU node. 3) Added latest tags. Changes since v1: 1) As per Igor's suggestion, migrated fw_cfg and virtio creation functions to device specific file instead of generic aml-build.c. Since ACPI is optional, new files are created and enabled for build only when CONFIG_ACPI is enabled. 2) As per Igor's suggestion, properties are added to the GPEX PCI host to indicate MMIO ranges. The platform fw can initialize these to appropriate values and the DSDT generator can fetch the information from the host bus itself. This makes the code generic instead of machine specific. 3) Added PLIC patch from Haibo. 4) Rebased to latest riscv-to-apply.next and added RB tags as appropriate. Sunil V L (13): hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location hw/arm/virt-acpi-build.c: Migrate virtio creation to common location hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT hw/riscv: virt: Make few IMSIC macros and functions public hw/riscv/virt-acpi-build.c: Add AIA support in RINTC hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT hw/riscv/virt-acpi-build.c: Add APLIC in the MADT hw/riscv/virt-acpi-build.c: Add CMO information in RHCT hw/riscv/virt-acpi-build.c: Add MMU node in RHCT hw/pci-host/gpex: Define properties for MMIO ranges hw/riscv/virt: Update GPEX MMIO related properties hw/riscv/virt-acpi-build.c: Add IO controllers and devices hw/riscv/virt-acpi-build.c: Add PLIC in MADT hw/arm/virt-acpi-build.c | 51 +---- hw/i386/acpi-microvm.c | 15 +- hw/nvram/fw_cfg-acpi.c | 44 ++++ hw/nvram/meson.build | 1 + hw/pci-host/gpex-acpi.c | 13 ++ hw/pci-host/gpex.c | 12 ++ hw/riscv/Kconfig | 1 + hw/riscv/virt-acpi-build.c | 344 +++++++++++++++++++++++++++++--- hw/riscv/virt.c | 72 +++---- hw/virtio/meson.build | 1 + hw/virtio/virtio-acpi.c | 32 +++ include/hw/nvram/fw_cfg_acpi.h | 15 ++ include/hw/pci-host/gpex.h | 28 ++- include/hw/riscv/virt.h | 26 +++ include/hw/virtio/virtio-acpi.h | 17 ++ 15 files changed, 541 insertions(+), 131 deletions(-) create mode 100644 hw/nvram/fw_cfg-acpi.c create mode 100644 hw/virtio/virtio-acpi.c create mode 100644 include/hw/nvram/fw_cfg_acpi.h create mode 100644 include/hw/virtio/virtio-acpi.h