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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id nv18-20020a17090b1b5200b0027fee011cebsm1326061pjb.10.2023.10.26.08.18.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 08:18:38 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou Subject: [PATCH v2 00/14] Update RISC-V vector crypto to ratified v1.0.0 Date: Thu, 26 Oct 2023 23:18:07 +0800 Message-Id: <20231026151828.754279-1-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=max.chou@sifive.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patchset updates the RISC-V vector cryptography support to the ratified version v1.0.0 (commit 1769c26, released on 2023/10). v2: - Fixed the instruction order at disassembler part. - Fixed the vror.vi disassembler format. - Verified by code examples provided by vector crypto spec repository (riscv-crypto). - Rebased to riscv-to-apply.next branch (1f910f3) v1: - Support Zvkb, Zvkt, and other shorthand extensions(Zvkn, Zvknc, Zvkng, Zvks, Zvksc, Zvksg). - Support the disassembler for vector crypto extensions. - Moved vector crypto extensions from experimental extensions to ratified extensions. - Replaced TAB indentations with spaces in disas/riscv.c. Max Chou (14): target/riscv: Add cfg property for Zvkt extension target/riscv: Expose Zvkt extension property target/riscv: Add cfg property for Zvkb extension target/riscv: Replace Zvbb checking by Zvkb target/riscv: Expose Zvkb extension property target/riscv: Add cfg properties for Zvkn[c|g] extensions target/riscv: Expose Zvkn[c|g] extnesion properties target/riscv: Add cfg properties for Zvks[c|g] extensions target/riscv: Expose Zvks[c|g] extnesion properties target/riscv: Move vector crypto extensions to riscv_cpu_extensions disas/riscv: Add rv_fmt_vd_vs2_uimm format disas/riscv: Add rv_codec_vror_vi for vror.vi disas/riscv: Add support for vector crypto extensions disas/riscv: Replace TABs with space disas/riscv.c | 157 ++++++++++++++++++++++- disas/riscv.h | 2 + target/riscv/cpu.c | 36 ++++-- target/riscv/cpu_cfg.h | 8 ++ target/riscv/insn_trans/trans_rvvk.c.inc | 37 ++++-- target/riscv/tcg/tcg-cpu.c | 48 ++++++- 6 files changed, 258 insertions(+), 30 deletions(-)