From patchwork Fri Nov 3 03:16:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 13444295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF235C001B0 for ; Fri, 3 Nov 2023 03:19:12 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qykgI-0007iy-Fq; Thu, 02 Nov 2023 23:17:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qykgB-0007hk-OG for qemu-devel@nongnu.org; Thu, 02 Nov 2023 23:17:07 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qykg9-0003Bh-P0 for qemu-devel@nongnu.org; Thu, 02 Nov 2023 23:17:03 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-6c0f14d6875so1669116b3a.1 for ; Thu, 02 Nov 2023 20:17:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1698981420; x=1699586220; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=pSo8/xWA1h+NiRRDtSfTewm0FT3ASIneHMhutcA3mhY=; b=htzUSw0ZV7BQWb63bnBg0l1vaDbnUG05f8FqNMKqU1lk8I5S+FTYVGKSnOfCJRrwMp j0qoAHca7E//XP93B+M3ENX1ugfu0kRiPu8jBwPVmBM8O1qOvYQ/QJv3jIJlFTA6rgKs nsGgtlGW8qnFhDm5Ub1oE2prUcf4iJt7dP+TMc2oZvdgE47kk1407tMpdUR1jdByw4X4 IdxTCH9GfUtEdVqh3uiPZSELyM0zff7c5iiGQfzDDPYMQRFweLbLyxFrciw7qs6hE+C2 k1URYdyj4s+JP2Bly3EzyD4PR5nWK6lG/Dhgiqciu4J+691wpbF8kQb7SkKxo5XePvOi JqnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698981420; x=1699586220; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=pSo8/xWA1h+NiRRDtSfTewm0FT3ASIneHMhutcA3mhY=; b=WYSYFZOkj4vAQV5q5WJ/eMdYtU7+v0X69oO5ivrFVM32RV9qG3kDDrMKj6IaldELbE iqbqR/E5jg/Zb7359rnyBcMqFOG3yqwX2yeFCGRYJt4iS6inYniZfs4d8G0IkzM/U0+5 lwkYjbJsq0HwsfEWAKeYTAAAIsmKMc0QBGRX0AwwmK6d+yueoA+644z2wWshSibId1wV 5+f7YZK0fa2L02iPq/9mUssOBDxJKARJ4YQ02J2aDWpeoP0Tp1QKX04eJOw4TOLpiNl2 nZL694+gTMmW+0fM4KQPQUeSY/XdsgwNBLGuCglgpynDGIUknVqvodFnqz49SU6bUgbU TsRA== X-Gm-Message-State: AOJu0YzrhaFYs6a35rUTqbcK0h+Sq45oVucenX4apgQA+KewPUgyHxdv FLsyoEuuve1kzG7PimnNKYRWYA== X-Google-Smtp-Source: AGHT+IEuO0WlR/5QnZ05uMhD5SWdHMsZ1jo3+MFECyb8xZvdLKGurDjlRoW02UiNtJjvW13yq45Rig== X-Received: by 2002:a05:6a20:1453:b0:152:6b63:f1e7 with SMTP id a19-20020a056a20145300b001526b63f1e7mr20008900pzi.1.1698981419699; Thu, 02 Nov 2023 20:16:59 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id y17-20020a17090aca9100b0027cf4c554dasm499971pjt.11.2023.11.02.20.16.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 20:16:59 -0700 (PDT) From: Sunil V L To: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Peter Maydell , Shannon Zhao , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Gerd Hoffmann , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Anup Patel , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [PATCH v7 00/13] RISC-V: ACPI: Enable AIA, PLIC and update RHCT Date: Fri, 3 Nov 2023 08:46:36 +0530 Message-Id: <20231103031649.2769834-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=sunilvl@ventanamicro.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series primarily enables external interrupt controllers (AIA and PLIC) in ACPI tables for RISC-V virt platform. It also updates RHCT with CMO and MMU related information. Below ECRs for these changes are approved by ASWG and will be available in next ACPI spec release. 1) MADT (AIA) - https://drive.google.com/file/d/1oMGPyOD58JaPgMl1pKasT-VKsIKia7zR/view?usp=sharing 2) RHCT - https://drive.google.com/file/d/1sKbOa8m1UZw1JkquZYe3F1zQBN1xXsaf/view?usp=sharing First two patches in this series are to migrate a couple of functions from ARM architecture to common code so that RISC-V doesn't need to duplicate the same. The patch set is based on Alistair's riscv-to-apply.next branch. These changes are also available in riscv_acpi_b2_v7 branch at: https://github.com/vlsunil/qemu/ Changes since v6: 1) Fixed the qtest failure issue reported by Daniel in PATCH 2. Changes since v5: 1) Fixed the issue in PATCH 2 reported by Daniel found when built with clang + --enable-debug. Changes since v4: 1) Updated copyright for new files as per SPDX format suggested by Drew. 2) Updated RINTC patch to avoid code duplication as suggested by Drew. 3) Moved mmu offset below cmo in MMU patch as suggested by Drew. 4) Updated tags. Changes since v3: 1) Addressed comments from Daniel and Drew. 2) Added a new patch in microvm to use common function for virtio in DSDT. 3) Rebased to latest riscv-to-apply.next branch and added tags. Changes since v2: 1) Rebased to latest riscv-to-apply.next branch which needed changing ext_icboz to ext_zicboz in CMO patch. 2) Fixed node type in MMU node. 3) Added latest tags. Changes since v1: 1) As per Igor's suggestion, migrated fw_cfg and virtio creation functions to device specific file instead of generic aml-build.c. Since ACPI is optional, new files are created and enabled for build only when CONFIG_ACPI is enabled. 2) As per Igor's suggestion, properties are added to the GPEX PCI host to indicate MMIO ranges. The platform fw can initialize these to appropriate values and the DSDT generator can fetch the information from the host bus itself. This makes the code generic instead of machine specific. 3) Added PLIC patch from Haibo. 4) Rebased to latest riscv-to-apply.next and added RB tags as appropriate. Sunil V L (13): hw/arm/virt-acpi-build.c: Migrate fw_cfg creation to common location hw/arm/virt-acpi-build.c: Migrate virtio creation to common location hw/i386/acpi-microvm.c: Use common function to add virtio in DSDT hw/riscv: virt: Make few IMSIC macros and functions public hw/riscv/virt-acpi-build.c: Add AIA support in RINTC hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT hw/riscv/virt-acpi-build.c: Add APLIC in the MADT hw/riscv/virt-acpi-build.c: Add CMO information in RHCT hw/riscv/virt-acpi-build.c: Add MMU node in RHCT hw/pci-host/gpex: Define properties for MMIO ranges hw/riscv/virt: Update GPEX MMIO related properties hw/riscv/virt-acpi-build.c: Add IO controllers and devices hw/riscv/virt-acpi-build.c: Add PLIC in MADT hw/arm/virt-acpi-build.c | 51 +---- hw/i386/acpi-microvm.c | 15 +- hw/nvram/fw_cfg-acpi.c | 23 +++ hw/nvram/meson.build | 1 + hw/pci-host/gpex-acpi.c | 13 ++ hw/pci-host/gpex.c | 12 ++ hw/riscv/Kconfig | 1 + hw/riscv/virt-acpi-build.c | 323 +++++++++++++++++++++++++++++--- hw/riscv/virt.c | 72 ++++--- hw/virtio/meson.build | 1 + hw/virtio/virtio-acpi.c | 33 ++++ include/hw/nvram/fw_cfg_acpi.h | 15 ++ include/hw/pci-host/gpex.h | 28 ++- include/hw/riscv/virt.h | 26 +++ include/hw/virtio/virtio-acpi.h | 16 ++ 15 files changed, 499 insertions(+), 131 deletions(-) create mode 100644 hw/nvram/fw_cfg-acpi.c create mode 100644 hw/virtio/virtio-acpi.c create mode 100644 include/hw/nvram/fw_cfg_acpi.h create mode 100644 include/hw/virtio/virtio-acpi.h