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([179.193.10.161]) by smtp.gmail.com with ESMTPSA id j68-20020a0df947000000b00582b239674esm935814ywf.129.2023.11.03.06.46.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 06:46:34 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v10 00/18] rv64i and rva22u64 CPUs, RVA22U64 profile support Date: Fri, 3 Nov 2023 10:46:11 -0300 Message-ID: <20231103134629.561732-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::112f; envelope-from=dbarboza@ventanamicro.com; helo=mail-yw1-x112f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This new version contains changes proposed by Drew in v9. The most notable change is the drop of the 'max' CPU profile restriction. Patches based on Alistair's riscv-to-apply.next. All patches acked. - patch 3: - move the 'priv_spec' comment to cpu_validate_multi_ext_priv_ver() right before the version is bumped - patch 4: - Fixed 'Bare CPUs' comment in set_satp_mode_default_map() - Changed rv64i_bare_cpu_init() comment to "Set to QEMU's first supported priv version" - patch 10: - removed 'priv_spec' comment from cpu_set_profile() - patch 18: - added a DEFINE_PROFILE_CPU() macro - renamed rva22u64_bare_cpu_init() to rva22u64_profile_cpu_init() - patch 19: dropped - v9 link: https://lore.kernel.org/qemu-riscv/20231102224445.527355-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (18): target/riscv: create TYPE_RISCV_VENDOR_CPU target/riscv/tcg: do not use "!generic" CPU checks target/riscv/tcg: update priv_ver on user_set extensions target/riscv: add rv64i CPU target/riscv: add zicbop extension flag target/riscv/tcg: add 'zic64b' support riscv-qmp-cmds.c: expose named features in cpu_model_expansion target/riscv: add rva22u64 profile definition target/riscv/kvm: add 'rva22u64' flag as unavailable target/riscv/tcg: add user flag for profile support target/riscv/tcg: add MISA user options hash target/riscv/tcg: add riscv_cpu_write_misa_bit() target/riscv/tcg: handle profile MISA bits target/riscv/tcg: add hash table insert helpers target/riscv/tcg: honor user choice for G MISA bits target/riscv/tcg: validate profiles during finalize riscv-qmp-cmds.c: add profile flags in cpu-model-expansion target/riscv: add 'rva22u64' CPU hw/riscv/virt.c | 5 + target/riscv/cpu-qom.h | 4 + target/riscv/cpu.c | 134 ++++++++++++- target/riscv/cpu.h | 13 ++ target/riscv/cpu_cfg.h | 3 + target/riscv/kvm/kvm-cpu.c | 7 +- target/riscv/riscv-qmp-cmds.c | 44 ++++- target/riscv/tcg/tcg-cpu.c | 350 ++++++++++++++++++++++++++++++---- 8 files changed, 507 insertions(+), 53 deletions(-)