[v5,0/3] pnv nest1 chiplet model

Message

Chalapathi V Nov. 24, 2023, 10:15 a.m. UTC

Hello,

Thank you for the review and suggestions on V4.

The suggestions and changes requested in V4 are considered and incorporated in
V5.

In this version, couple of powerbus scom registers are modelled.
Hence the new qom-tree is as below.
(qemu) info qom-tree 
/machine (powernv10-machine)
  /chip[0] (power10_v2.0-pnv-chip)
    /nest1 (pnv-nest1-chiplet)
      /perv (pnv-pervasive-chiplet)
        /xscom-nest1-control-regs[0] (memory-region)
      /xscom-nest1-pb-scom-eq-regs[0] (memory-region)
      /xscom-nest1-pb-scom-es-regs[0] (memory-region)

Patches overview in V5.
PATCH1: Create a common perv chiplet model with control chiplet scom registers
PATCH2: Create a nest1 chiplet model, connect perv model to nest1 and implement
        powerbus scom registers.
PATCH3: Connect nest1 model to p10 chip.

Test covered:
These changes are tested on a single socket and 2 socket P10 machine.

Thank You,
Chalapathi

Chalapathi V (3):
  hw/ppc: Add pnv pervasive common chiplet units
  hw/ppc: Add nest1 chiplet model
  hw/ppc: Nest1 chiplet wiring

 include/hw/ppc/pnv_chip.h         |   2 +
 include/hw/ppc/pnv_nest_chiplet.h |  36 +++++
 include/hw/ppc/pnv_pervasive.h    |  37 +++++
 include/hw/ppc/pnv_xscom.h        |   9 ++
 hw/ppc/pnv.c                      |  14 ++
 hw/ppc/pnv_nest1_chiplet.c        | 197 +++++++++++++++++++++++++++
 hw/ppc/pnv_pervasive.c            | 217 ++++++++++++++++++++++++++++++
 hw/ppc/meson.build                |   2 +
 8 files changed, 514 insertions(+)
 create mode 100644 include/hw/ppc/pnv_nest_chiplet.h
 create mode 100644 include/hw/ppc/pnv_pervasive.h
 create mode 100644 hw/ppc/pnv_nest1_chiplet.c
 create mode 100644 hw/ppc/pnv_pervasive.c