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Mon, 27 Nov 2023 17:13:12 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B18AE20040; Mon, 27 Nov 2023 17:13:10 +0000 (GMT) Received: from gfwr515.rchland.ibm.com (unknown [9.10.239.103]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 27 Nov 2023 17:13:10 +0000 (GMT) From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, chalapathi.v@linux.ibm.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v6 0/3] pnv nest1 chiplet model Date: Mon, 27 Nov 2023 11:13:04 -0600 Message-Id: <20231127171307.5237-1-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: GGmMISMgo6XjYI1F3riv06DlNsO6mObW X-Proofpoint-GUID: p0VVZQBiqlggkvojbFS4r3yLWig-f37m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-27_15,2023-11-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 mlxscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 mlxlogscore=638 phishscore=0 malwarescore=0 clxscore=1015 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311270119 Received-SPF: pass client-ip=148.163.158.5; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hello, Thank you for the review and suggestions on V5. The suggestions and changes requested from V5 are addressed in V6. Updates in Version 6 of this series are: 1. adding a device-tree node in QEMU is removed as skiboot defines the device-tree and QEMU should just follow it. 2. Renamed PnvPerv to PnvNestChipletPervasive in PATCH1 as the model provides the common pervasive registers of all nest chiplets. 3. Nest1_chiplet model in PATCH2 is renamed to N1_chiplet to avoid the confussions that may comeup later. Hence the new qom-tree looks like below. (qemu) info qom-tree /machine (powernv10-machine) /chip[0] (power10_v2.0-pnv-chip) /n1_chiplet (pnv-N1-chiplet) /nest_pervasive_common (pnv-nest-chiplet-pervasive) /xscom-n1_chiplet-control-regs[0] (memory-region) /xscom-n1_chiplet-pb-scom-eq-regs[0] (memory-region) /xscom-n1_chiplet-pb-scom-es-regs[0] (memory-region) Patches overview in V6. PATCH1: Create a common nest pervasive chiplet model with control chiplet scom registers. PATCH2: Create a N1 chiplet model and implement powerbus scom registers. Connect common nest pervasive model to N1 chiplet model to define chiplet control scoms for N1 chiplet. PATCH3: Connect N1 chiplet model to p10 chip. Test covered: These changes are tested on a single socket and 2 socket P10 machine. Thank You, Chalapathi Chalapathi V (3): hw/ppc: Add pnv nest pervasive common chiplet model hw/ppc: Add N1 chiplet model hw/ppc: N1 chiplet wiring include/hw/ppc/pnv_chip.h | 2 + include/hw/ppc/pnv_n1_chiplet.h | 35 +++++ include/hw/ppc/pnv_nest_pervasive.h | 36 +++++ include/hw/ppc/pnv_xscom.h | 9 ++ hw/ppc/pnv.c | 15 ++ hw/ppc/pnv_n1_chiplet.c | 171 ++++++++++++++++++++++ hw/ppc/pnv_nest_pervasive.c | 219 ++++++++++++++++++++++++++++ hw/ppc/meson.build | 2 + 8 files changed, 489 insertions(+) create mode 100644 include/hw/ppc/pnv_n1_chiplet.h create mode 100644 include/hw/ppc/pnv_nest_pervasive.h create mode 100644 hw/ppc/pnv_n1_chiplet.c create mode 100644 hw/ppc/pnv_nest_pervasive.c