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[77.13.84.64]) by smtp.gmail.com with ESMTPSA id z16-20020adfec90000000b003366fb71297sm30063183wrn.81.2024.01.03.00.49.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 00:49:13 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Richard Henderson , Paolo Bonzini , Marcel Apfelbaum , Eduardo Habkost , Bernhard Beschow Subject: [PATCH 0/2] Fix PIC interrupt handling of x86 CPUs if APIC is globally disabled Date: Wed, 3 Jan 2024 09:48:58 +0100 Message-ID: <20240103084900.22856-1-shentey@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=shentey@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This two-patch series is part of my work emulating the VIA Apollo Pro 133T chipset in QEMU [1] and testing it by running real-world BIOSes on it. The first patch fixes an issue regarding PIC interrupt handling, the second one just fixes a typo in a comment. During testing, I've found that the boot process gets stuck for some BIOSes that disable the LAPIC globally (by disabling the enable bit in the base address register). QEMU seems to emulate PIC interrupt handling only if a CPU doesn't have a LAPIC, and always emulates LAPIC interrupt handling if one is present. According to the Intel documentation, a CPU should resort to PIC interrupt handling if its LAPIC is globally didabled. This series fixes this corner case which makes the boot process succeed. More details can be found in the commit message. Testing done: * `make check` * `make check-avocado` [1] https://github.com/shentok/qemu/tree/via-apollo-pro-133t Bernhard Beschow (2): hw/i386/x86: Fix PIC interrupt handling if APIC globally disabled target/i386/cpu: Fix small typo in comment hw/i386/x86.c | 10 +++++----- target/i386/cpu.c | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-)