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([189.79.21.107]) by smtp.gmail.com with ESMTPSA id v3-20020aa78503000000b006d7f1ae421csm24042050pfn.145.2024.01.03.09.40.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 09:40:22 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, vladimir.isaev@syntacore.com, Daniel Henrique Barboza Subject: [PATCH v3 00/16] target/riscv: deprecate riscv_cpu_options[] Date: Wed, 3 Jan 2024 14:39:57 -0300 Message-ID: <20240103174013.147279-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, In v2, after Vladimir's feedback, the following major changes were made: - add default values in riscv_cpu_init() instead of doing gimmicks with setters and .set_default_value callbacks. The cost of having defaults for non-boolean properties in the parent class is smaller than having to deal with duplicated 'if cfg.prop == 0' checks in all setters; - all properties are now being registered in the 'general_user_opts' hash. We were registering only the properties that KVM checks, Vladimir pointed out that this isn't consistent, we're making it consistent now. Other smaller changes were made in patches 1, 2, 3 and 7. Vladimir, due to the amount of changes I didn't add your "Tested-by" in the patches. You're welcome to give this another try and add a tested-by again :) Patches based on riscv-to-apply.next. Changes from v2: - patch 1: - remove 'bext_ver' from cpu.h - patch 2 and 3: switched places - patch 3 (former 2): - added hash implementation from patch 8 - added pmu_mask setter() - pmu-mask and pmu-num can't be changed for vendor CPUs - patches 4, 5, 6: - properties are now being added in the hash - patch 7: - fixed string check in prop_vext_spec_set() - vext_spec is now being added in the hash - patches 8, 9, 11, 12: - default values added in riscv_cpu_init() - no longer checking for "value == 0" in setters - v2 link: https://lore.kernel.org/qemu-riscv/20231222122235.545235-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (16): target/riscv/cpu_cfg.h: remove unused fields target/riscv: make riscv_cpu_is_generic() public target/riscv: move 'pmu-mask' and 'pmu-num' to riscv_cpu_properties[] target/riscv: move 'mmu' to riscv_cpu_properties[] target/riscv: move 'pmp' to riscv_cpu_properties[] target/riscv: rework 'priv_spec' target/riscv: rework 'vext_spec' target/riscv: move 'vlen' to riscv_cpu_properties[] target/riscv: move 'elen' to riscv_cpu_properties[] target/riscv: create finalize_features() for KVM target/riscv: move 'cbom_blocksize' to riscv_cpu_properties[] target/riscv: move 'cboz_blocksize' to riscv_cpu_properties[] target/riscv: remove riscv_cpu_options[] target/riscv/cpu.c: move 'mvendorid' to riscv_cpu_properties[] target/riscv/cpu.c: move 'mimpid' to riscv_cpu_properties[] target/riscv/cpu.c: move 'marchid' to riscv_cpu_properties[] target/riscv/cpu.c | 614 ++++++++++++++++++++++++++++++----- target/riscv/cpu.h | 8 +- target/riscv/cpu_cfg.h | 4 - target/riscv/kvm/kvm-cpu.c | 94 +++--- target/riscv/kvm/kvm_riscv.h | 1 + target/riscv/tcg/tcg-cpu.c | 63 ---- 6 files changed, 590 insertions(+), 194 deletions(-)