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([189.79.22.11]) by smtp.gmail.com with ESMTPSA id b29-20020aa78edd000000b006db056542e6sm49151pfr.190.2024.01.08.08.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 08:19:12 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v2 0/2] riscv: add rv32i,rv32e and rv64e CPUs Date: Mon, 8 Jan 2024 13:19:01 -0300 Message-ID: <20240108161903.353648-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This is the second version of a buried patch series: "[PATCH for-9.0 0/6] riscv: rv32i,rv32e,rv64i and rv64e CPUs" This version shrank to 2 patches since most of the prep work was already done by the RVA22 profile implementation, which is now queued in riscv-to-apply.next. The motivation is the same as in v1 - give users a cleaner way of using a customized CPU, from scratch, without the need to disable default extensions. Patches based on Alistair's riscv-to-apply.next. Changes from v1: - patches 1 to 4 from v1: dropped - patches 5 and 6 from v1: merged into patch 2 - patch 1 (new): - add a new common cpu_init() for all bare CPUs - v1 link: https://lore.kernel.org/qemu-riscv/20231113213904.185320-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (2): target/riscv/cpu.c: add riscv_bare_cpu_init() target/riscv: add rv32i, rv32e and rv64e CPUs target/riscv/cpu-qom.h | 3 ++ target/riscv/cpu.c | 64 ++++++++++++++++++++++++++++++++---------- 2 files changed, 52 insertions(+), 15 deletions(-)