[v3,0/3] target/riscv: Add support for Zaamo & Zalrsc

Message

Rob Bradford Jan. 23, 2024, 11:10 a.m. UTC

Introduce support for the proposed new (fast-track) Zaamo and Zalrsc
extensions [1] which represent the AMO and LR/SC subsets of the A
extension. 

The motivation for the subsets being available separately is that
certain classes of CPUs may choose to only implement a subset for
architectural convenience.

Since this extension is not frozen these are advertised by "x-zaamo" and
"x-zalrsc" options. Beyond adding the extension infrastructure the only
changes required are to allow the atomic instructions under either A or
the appropriate subset extension.  To ensure compatibility enabling the
A instruction does not enable these two extensions - future hardware may
choose to advertise support for A and both these extensions for maximum
software support.

This patch is based off riscv-to-apply.next due to conflicts with
existing patches.

Cheers,

Rob

[1] - https://github.com/riscv/riscv-zaamo-zalrsc

Changes since V2:
- Split extension exposure from infrastructure (Alistair)

Changes since V1:
- Fix commit message that did not account for earlier fix (Daniel)

Rob Bradford (3):
  target/riscv: Add Zaamo and Zalrsc extension infrastructure
  target/riscv: Check 'A' and split extensions for atomic instructions
  target/riscv: Expose Zaamo and Zalrsc extensions

 target/riscv/cpu.c                      |  5 +++
 target/riscv/cpu_cfg.h                  |  2 +
 target/riscv/insn_trans/trans_rva.c.inc | 56 +++++++++++++++----------
 3 files changed, 41 insertions(+), 22 deletions(-)