[0/5,qemu] hw/cxl: Update CXL emulation to reflect and reference r3.1

Message

Jonathan Cameron Jan. 24, 2024, 1:48 p.m. UTC

Last year a reviewer requested that the versioning and references in the CXL
code pointed out at a specific available specification revision (Sorry I can't
remember who!)  That drew my attention to the complete mess of versioning
with many comments not calling out which version of CXL they were refering
to (these date back to when we only cared about CXL r2.0)

Unfortunately without being a CXL consortium member only one version of
the specification is easily obtained (via a click through for 'evaluation'
purposes) from https://www.computeexpresslink.org/download-the-specification .
Whilst I hope that will change, given we need to clean this up anyway
it make sense to standardize on CXL r3.1 which is the currently available
version.  Note that I have no intentioning of doing this again for
CXL rNext when it appears - this is intended to be a onetime thing.

Some structures have been updated between when we introduced the emulation
of a particular feature and today, but this has been done in a backwards
compatible way. So to bring everything up to CXL revision 3.1, I've added
definitions etc for new fields and registers, but set the capability bits
to say we don't support anything they tell us about and write masks should
leave the control bits reserved (e.g. not writeable)

This will result in a small amount of register placement changing but
it's all discoverable and the CXL emulation doesn't currently allow
sensible migration anyway, we shouldn't have any backwards compatibility
problems.

For those kind enough to review, given this involves some tedious spec
diving, feel free to do a subset and state what you covered so that
others can avoid duplication.

Based-on: [PATCH 00/12 qemu] CXL emulation fixes and minor cleanup.

Based-on: Message-ID: [e-mail]

Jonathan Cameron (5):
  hw/cxl: Update HDM Decoder capability to version 3
  hw/cxl: Update link register definitions.
  hw/cxl: Update RAS Capability Definitions for version 3.
  hw/cxl: Update mailbox status registers.
  hw/cxl: Standardize all references on CXL r3.1 and minor updates

 docs/system/devices/cxl.rst    |  3 +-
 include/hw/cxl/cxl_cdat.h      | 10 ++---
 include/hw/cxl/cxl_component.h | 51 +++++++++++++++-------
 include/hw/cxl/cxl_device.h    | 77 +++++++++++++++++++++++-----------
 include/hw/cxl/cxl_events.h    | 18 ++++----
 include/hw/cxl/cxl_pci.h       | 67 ++++++++++++++++++++---------
 hw/cxl/cxl-component-utils.c   | 29 ++++++++-----
 hw/cxl/cxl-device-utils.c      | 14 +++++--
 hw/cxl/cxl-events.c            |  2 +-
 hw/cxl/cxl-mailbox-utils.c     | 49 ++++++++++++----------
 hw/mem/cxl_type3.c             |  6 +--
 hw/pci-bridge/cxl_downstream.c |  4 +-
 hw/pci-bridge/cxl_root_port.c  |  4 +-
 hw/pci-bridge/cxl_upstream.c   |  4 +-
 14 files changed, 219 insertions(+), 119 deletions(-)