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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id x16-20020aa7d390000000b0055c2b21be1dsm600205edq.35.2024.01.26.05.31.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 05:31:02 -0800 (PST) From: Andrew Jones To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, dbarboza@ventanamicro.com Subject: [PATCH v2 0/6] riscv: named features riscv,isa, 'svade' rework Date: Fri, 26 Jan 2024 14:31:02 +0100 Message-ID: <20240126133101.61344-8-ajones@ventanamicro.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-type: text/plain Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=ajones@ventanamicro.com; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This is a bundle of fixes based on discoveries that were made in the last week or so: - what we call "named features" are actually real extensions, which are considered to be ratified by the profile spec that defines them. This means that we need to add riscv,isa strings for them. More info can be found on the commit msg of patch 2; - the design behind 'svade' and 'svadu' is wrong. 'svade' does not mean 'we do not have svadu'. In fact they can coexist. Patch 5 gives more details about it. After this series, 'svade' is promoted to a regular extension and all the named features QEMU implements are now being displayed in riscv,isa. v2: - Ensure svade is off by default even for the max cpu type Andrew Jones (3): target/riscv: Reset henvcfg to zero target/riscv: Gate hardware A/D PTE bit updating target/riscv: Promote svade to a normal extension Daniel Henrique Barboza (3): target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() target/riscv: add riscv,isa to named features target/riscv: add remaining named features target/riscv/cpu.c | 63 ++++++++++++++++++++++++++++---------- target/riscv/cpu_cfg.h | 15 +++++++-- target/riscv/cpu_helper.c | 18 ++++++++--- target/riscv/csr.c | 2 +- target/riscv/tcg/tcg-cpu.c | 48 +++++++++++++++++++---------- 5 files changed, 105 insertions(+), 41 deletions(-)