[0/4] RISC-V: Implement CSR tcontrol in debug spec

Message

Alvin Che-Chia Chang(張哲嘉) Feb. 16, 2024, 6:13 a.m. UTC

The RISC-V Debug specification defines CSR "tcontrol" in the trigger
module:
  https://github.com/riscv/riscv-debug-spec

This series implements it and the related operations.

Alvin Chang (4):
  target/riscv: Add CSR tcontrol of debug trigger module
  target/riscv: Reset CSR tcontrol when the trigger module resets
  target/riscv: Set the value of CSR tcontrol when trapping to M-mode
  target/riscv: Set the value of CSR tcontrol when mret is executed

 target/riscv/cpu.h        |  1 +
 target/riscv/cpu_bits.h   |  3 +++
 target/riscv/cpu_helper.c |  6 ++++++
 target/riscv/csr.c        | 15 +++++++++++++++
 target/riscv/debug.c      |  1 +
 target/riscv/op_helper.c  |  6 ++++++
 6 files changed, 32 insertions(+)