| Message ID | 20240227012405.71650-1-alvinga@andestech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | RISC-V: Modularize common match conditions for trigger | expand |
Hi Alistair, Please also take a look at this series, I guess it is ready to be applied, thanks! BRs, Alvin > -----Original Message----- > From: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> > Sent: Tuesday, February 27, 2024 9:24 AM > To: qemu-riscv@nongnu.org; qemu-devel@nongnu.org > Cc: alistair.francis@wdc.com; bin.meng@windriver.com; > liwei1518@gmail.com; dbarboza@ventanamicro.com; > zhiwei_liu@linux.alibaba.com; Alvin Che-Chia Chang(張哲嘉) > <alvinga@andestech.com> > Subject: [PATCH v4 0/4] RISC-V: Modularize common match conditions for > trigger > > According to RISC-V Debug specification ratified version 0.13 [1] (also applied > to version 1.0 [2] but it has not been ratified yet), the enabled privilege levels > of the trigger is common match conditions for all the types of the trigger. > > This series modularize the code for checking the privilege levels of type 2/3/6 > triggers by implementing functions trigger_common_match() and > trigger_priv_match(). > > Additional match conditions, such as CSR tcontrol and textra, can be further > implemented into trigger_common_match() in the future. > > [1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote > [2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc > > Changes from v3: > - Change this series to target Debug Spec. version 0.13 > > Changes from v2: > - Explicitly mention the targeting version of RISC-V Debug Spec. > > Changes from v1: > - Fix typo > - Add commit description for changing behavior of looping the triggers > when we check type 2 triggers. > > Alvin Chang (4): > target/riscv: Add functions for common matching conditions of trigger > target/riscv: Apply modularized matching conditions for breakpoint > target/riscv: Apply modularized matching conditions for watchpoint > target/riscv: Apply modularized matching conditions for icount trigger > > target/riscv/debug.c | 124 +++++++++++++++++++++++++++++-------------- > 1 file changed, 83 insertions(+), 41 deletions(-) > > -- > 2.34.1 CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.
On Thu, Mar 7, 2024 at 12:36 PM Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> wrote: > > Hi Alistair, > > Please also take a look at this series, I guess it is ready to be applied, thanks! This is all acked now, do you mind rebasing on https://github.com/alistair23/qemu/tree/riscv-to-apply.next and sending a new version Alistair > > > BRs, > Alvin > > > -----Original Message----- > > From: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> > > Sent: Tuesday, February 27, 2024 9:24 AM > > To: qemu-riscv@nongnu.org; qemu-devel@nongnu.org > > Cc: alistair.francis@wdc.com; bin.meng@windriver.com; > > liwei1518@gmail.com; dbarboza@ventanamicro.com; > > zhiwei_liu@linux.alibaba.com; Alvin Che-Chia Chang(張哲嘉) > > <alvinga@andestech.com> > > Subject: [PATCH v4 0/4] RISC-V: Modularize common match conditions for > > trigger > > > > According to RISC-V Debug specification ratified version 0.13 [1] (also applied > > to version 1.0 [2] but it has not been ratified yet), the enabled privilege levels > > of the trigger is common match conditions for all the types of the trigger. > > > > This series modularize the code for checking the privilege levels of type 2/3/6 > > triggers by implementing functions trigger_common_match() and > > trigger_priv_match(). > > > > Additional match conditions, such as CSR tcontrol and textra, can be further > > implemented into trigger_common_match() in the future. > > > > [1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote > > [2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc > > > > Changes from v3: > > - Change this series to target Debug Spec. version 0.13 > > > > Changes from v2: > > - Explicitly mention the targeting version of RISC-V Debug Spec. > > > > Changes from v1: > > - Fix typo > > - Add commit description for changing behavior of looping the triggers > > when we check type 2 triggers. > > > > Alvin Chang (4): > > target/riscv: Add functions for common matching conditions of trigger > > target/riscv: Apply modularized matching conditions for breakpoint > > target/riscv: Apply modularized matching conditions for watchpoint > > target/riscv: Apply modularized matching conditions for icount trigger > > > > target/riscv/debug.c | 124 +++++++++++++++++++++++++++++-------------- > > 1 file changed, 83 insertions(+), 41 deletions(-) > > > > -- > > 2.34.1 > > CONFIDENTIALITY NOTICE: > > This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. > > Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.
> -----Original Message----- > From: Alistair Francis <alistair23@gmail.com> > Sent: Tuesday, June 4, 2024 9:58 AM > To: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> > Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org; > alistair.francis@wdc.com; bin.meng@windriver.com; liwei1518@gmail.com; > dbarboza@ventanamicro.com; zhiwei_liu@linux.alibaba.com > Subject: Re: [PATCH v4 0/4] RISC-V: Modularize common match conditions for > trigger > > [EXTERNAL MAIL] > > On Thu, Mar 7, 2024 at 12:36 PM Alvin Che-Chia Chang(張哲嘉) > <alvinga@andestech.com> wrote: > > > > Hi Alistair, > > > > Please also take a look at this series, I guess it is ready to be applied, thanks! > > This is all acked now, do you mind rebasing on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next and sending a new > version Done, please check patch v5. I also took care of Daniel's latest patch: https://github.com/alistair23/qemu/commit/0099f6053410f5611796213b723e908cfc8055eb BRs, Alvin > > Alistair > > > > > > > BRs, > > Alvin > > > > > -----Original Message----- > > > From: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> > > > Sent: Tuesday, February 27, 2024 9:24 AM > > > To: qemu-riscv@nongnu.org; qemu-devel@nongnu.org > > > Cc: alistair.francis@wdc.com; bin.meng@windriver.com; > > > liwei1518@gmail.com; dbarboza@ventanamicro.com; > > > zhiwei_liu@linux.alibaba.com; Alvin Che-Chia Chang(張哲嘉) > > > <alvinga@andestech.com> > > > Subject: [PATCH v4 0/4] RISC-V: Modularize common match conditions > > > for trigger > > > > > > According to RISC-V Debug specification ratified version 0.13 [1] > > > (also applied to version 1.0 [2] but it has not been ratified yet), > > > the enabled privilege levels of the trigger is common match conditions for > all the types of the trigger. > > > > > > This series modularize the code for checking the privilege levels of > > > type 2/3/6 triggers by implementing functions trigger_common_match() > > > and trigger_priv_match(). > > > > > > Additional match conditions, such as CSR tcontrol and textra, can be > > > further implemented into trigger_common_match() in the future. > > > > > > [1]: > > > https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vo > > > te > > > [2]: > > > https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asc > > > iidoc > > > > > > Changes from v3: > > > - Change this series to target Debug Spec. version 0.13 > > > > > > Changes from v2: > > > - Explicitly mention the targeting version of RISC-V Debug Spec. > > > > > > Changes from v1: > > > - Fix typo > > > - Add commit description for changing behavior of looping the triggers > > > when we check type 2 triggers. > > > > > > Alvin Chang (4): > > > target/riscv: Add functions for common matching conditions of trigger > > > target/riscv: Apply modularized matching conditions for breakpoint > > > target/riscv: Apply modularized matching conditions for watchpoint > > > target/riscv: Apply modularized matching conditions for icount > > > trigger > > > > > > target/riscv/debug.c | 124 > > > +++++++++++++++++++++++++++++-------------- > > > 1 file changed, 83 insertions(+), 41 deletions(-) > > > > > > -- > > > 2.34.1 > > > > CONFIDENTIALITY NOTICE: > > > > This e-mail (and its attachments) may contain confidential and legally > privileged information or information protected from disclosure. If you are not > the intended recipient, you are hereby notified that any disclosure, copying, > distribution, or use of the information contained herein is strictly prohibited. In > this case, please immediately notify the sender by return e-mail, delete the > message (and any accompanying documents) and destroy all printed hard > copies. Thank you for your cooperation. > > > > Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved. CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.