From patchwork Wed Feb 28 09:29:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jinjie Ruan X-Patchwork-Id: 13575110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2E9A7C47DD9 for ; Wed, 28 Feb 2024 09:32:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rfGHV-00017Q-Vr; Wed, 28 Feb 2024 04:31:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rfGHJ-00010x-Nu; Wed, 28 Feb 2024 04:31:07 -0500 Received: from szxga02-in.huawei.com ([45.249.212.188]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rfGHG-0001OW-1t; Wed, 28 Feb 2024 04:31:05 -0500 Received: from mail.maildlp.com (unknown [172.19.88.105]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4Tl8GB3y96zLqld; Wed, 28 Feb 2024 17:30:10 +0800 (CST) Received: from kwepemi500008.china.huawei.com (unknown [7.221.188.139]) by mail.maildlp.com (Postfix) with ESMTPS id BD1BC1402E2; Wed, 28 Feb 2024 17:30:49 +0800 (CST) Received: from huawei.com (10.67.174.55) by kwepemi500008.china.huawei.com (7.221.188.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Wed, 28 Feb 2024 17:30:49 +0800 To: , , , , , , CC: Subject: [RFC PATCH v4 00/22] target/arm: Implement FEAT_NMI and FEAT_GICv3_NMI Date: Wed, 28 Feb 2024 09:29:24 +0000 Message-ID: <20240228092946.1768728-1-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.67.174.55] X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To kwepemi500008.china.huawei.com (7.221.188.139) Received-SPF: pass client-ip=45.249.212.188; envelope-from=ruanjinjie@huawei.com; helo=szxga02-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jinjie Ruan X-Patchwork-Original-From: Jinjie Ruan via From: Jinjie Ruan Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch set implements FEAT_NMI and FEAT_GICv3_NMI for armv8. These introduce support for a new category of interrupts in the architecture which we can use to provide NMI like functionality. There are two modes for using this FEAT_NMI. When PSTATE.ALLINT or PSTATE.SP & SCTLR_ELx.SCTLR_SPINTMASK is set, any entry to ELx causes all interrupts including those with superpriority to be masked on entry to ELn until the mask is explicitly removed by software or hardware. PSTATE.ALLINT can be managed by software using the new register control ALLINT.ALLINT. Independent controls are provided for this feature at each EL, usage at EL1 should not disrupt EL2 or EL3. I have tested it with the following linux patches which try to support FEAT_NMI in linux kernel: https://lore.kernel.org/linux-arm-kernel/Y4sH5qX5bK9xfEBp@lpieralisi/T/#mb4ba4a2c045bf72c10c2202c1dd1b82d3240dc88 In the test, SGI, PPI and SPI interrupts can all be set to have super priority to be converted to a hardware NMI interrupt. The SGI is tested with kernel IPI as NMI framework, softlockup, hardlockup and kgdb test cases, and the PPI interrupt is tested with "perf top" command with hardware NMI enabled, and the SPI interrupt is tested with a custom test module, in which NMI interrupts can be received and sent normally. However, the Virtual NMI(VNMI) has not been tested. +-------------------------------------------------+ | Distributor | +-------------------------------------------------+ SPI | NMI | NMI \/ \/ +--------+ +-------+ | Redist | | Redist| +--------+ +-------+ SGI | NMI PPI | NMI \/ \/ +-------------+ +---------------+ |CPU Interface| ... | CPU Interface | +-------------+ +---------------+ | NMI | NMI \/ \/ +-----+ +-----+ | PE | | PE | +-----+ +-----+ Changes in v4: - Handle VNMI within the CPU and the GIC. - Keep PSTATE.ALLINT in env->pstate but not env->allint. - Fix the ALLINT MSR (immediate) decodetree implementation. - Accept NMI unconditionally for arm_cpu_has_work() but add comment. - Improve nmi mask in arm_excp_unmasked(). - Make the GICR_INMIR0 and GICD_INMIR implementation more clearer. - Improve ICC_NMIAR1_EL1 implementation - Extract gicv3_get_priority() to avoid priority code repetition. - Add Reviewed-by. Changes in v3: - Remove the FIQ NMI. - Adjust the patches Sequence. - Reomve the patch "Set pstate.ALLINT in arm_cpu_reset_hold". - Check whether support FEAT_NMI and FEAT_GICv3 for FEAT_GICv3_NMI. - With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set. - Not include NMI logic when FEAT_NMI or SCTLR_ELx.NMI not enabled. - Refator nmi mask in arm_excp_unmasked(). - Add VNMI definitions, add HCRX_VINMI and HCRX_VFNMI support in HCRX_EL2. - Add Reviewed-by and Acked-by. - Update the commit message. Changes in v2: - Break up the patches so that each one does only one thing. - Remove the command line option and just implement it in "max" cpu. Jinjie Ruan (22): target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI target/arm: Add PSTATE.ALLINT target/arm: Add support for FEAT_NMI, Non-maskable Interrupt target/arm: Implement ALLINT MSR (immediate) target/arm: Support MSR access to ALLINT target/arm: Add support for Non-maskable Interrupt target/arm: Add support for NMI in arm_phys_excp_target_el() target/arm: Handle IS/FS in ISR_EL1 for NMI target/arm: Handle PSTATE.ALLINT on taking an exception hw/arm/virt: Wire NMI and VNMI irq lines from GIC to CPU hw/intc/arm_gicv3: Add external IRQ lines for NMI target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64() hw/intc/arm_gicv3: Add irq superpriority information hw/intc/arm_gicv3_redist: Implement GICR_INMIR0 hw/intc/arm_gicv3: Implement GICD_INMIR hw/intc: Enable FEAT_GICv3_NMI Feature hw/intc/arm_gicv3: Add NMI handling CPU interface registers hw/intc/arm_gicv3: Implement NMI interrupt prioirty hw/intc/arm_gicv3: Report the NMI interrupt in gicv3_cpuif_update() hw/intc/arm_gicv3: Report the VNMI interrupt target/arm: Add FEAT_NMI to max hw/arm/virt: Add FEAT_GICv3_NMI feature support in virt GIC docs/system/arm/emulation.rst | 1 + hw/arm/virt.c | 25 ++++++++- hw/intc/arm_gicv3.c | 71 +++++++++++++++++++++--- hw/intc/arm_gicv3_common.c | 7 +++ hw/intc/arm_gicv3_cpuif.c | 77 ++++++++++++++++++++++++-- hw/intc/arm_gicv3_dist.c | 36 ++++++++++++ hw/intc/arm_gicv3_redist.c | 19 +++++++ hw/intc/gicv3_internal.h | 6 ++ hw/intc/trace-events | 1 + include/hw/intc/arm_gic_common.h | 2 + include/hw/intc/arm_gicv3_common.h | 7 +++ target/arm/cpu-features.h | 5 ++ target/arm/cpu-qom.h | 4 +- target/arm/cpu.c | 88 ++++++++++++++++++++++++++++-- target/arm/cpu.h | 8 +++ target/arm/helper.c | 73 +++++++++++++++++++++++++ target/arm/internals.h | 13 +++++ target/arm/tcg/a64.decode | 1 + target/arm/tcg/cpu64.c | 1 + target/arm/tcg/helper-a64.c | 16 ++++++ target/arm/tcg/helper-a64.h | 1 + target/arm/tcg/translate-a64.c | 19 +++++++ 22 files changed, 460 insertions(+), 21 deletions(-)