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([177.94.15.159]) by smtp.gmail.com with ESMTPSA id d3-20020a170902b70300b001dd66e6ec91sm107702pls.140.2024.03.08.13.54.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 13:54:12 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, richard.henderson@linaro.org, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v8 00/10] riscv: set vstart_eq_zero on mark_vs_dirty Date: Fri, 8 Mar 2024 18:53:40 -0300 Message-ID: <20240308215402.117405-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.43.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, In this new version we addressed the points rose by LIU Zhiwei in the v7 version. Some patches had to go, additional patches were added: - patches 1 and 2 from v7: already queued and sent in the last PR. - patch 6 from v7: moved to patch 1 - patches 2, 3, 4 and 5 (all new): rework how we update tail elements Version 7 has a problem with tail elements being updated regardless of vstart >= vl because there's no guard for it. To fix that, and be able to remove the the vstart >= vl brconds from the translation code (most of them - more on that later), we changed vext_set_tail_elems_1s() to be a no-op if vstart >= vl. After that we went through all the code that was setting tail elems with vext_set_elems_1s() and converted it to use vext_set_tail_elems_1s(). We'll not update tail elements if vstart >= vl even without a brcond guard in the translation code. - patch 6 (new): fix scalar move insns. They weren't setting vstart = 0. - patch 7 (patch 3 from v7): do not remove brconds from scalar move insns trans_vmv_s_x() and trans_vfmv_s_f() does not have a helper that will handle vstart >= vl for them, so they need their brcond. - patches 4 and 5 from v7: dropped. We're not removing all brconds, so we can't get rid of cpu_vstart and cpu_vl. Series based on alistair/riscv-to-apply.next. Patches missing review: 2, 3, 4, 5, 6. Daniel Henrique Barboza (9): target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() target/riscv: handle vstart >= vl in vext_set_tail_elems_1s() target/riscv/vector_helper.c: do vstart=0 after updating tail target/riscv/vector_helper.c: update tail with vext_set_tail_elems_1s() target/riscv: use vext_set_tail_elems_1s() in vcrypto insns trans_rvv.c.inc: set vstart = 0 in int scalar move insns target/riscv: remove 'over' brconds from vector trans trans_rvv.c.inc: remove redundant mark_vs_dirty() calls target/riscv/vector_helper.c: optimize loops in ldst helpers Ivan Klokov (1): target/riscv: Clear vstart_qe_zero flag target/riscv/insn_trans/trans_rvbf16.c.inc | 18 +- target/riscv/insn_trans/trans_rvv.c.inc | 205 ++++++--------------- target/riscv/insn_trans/trans_rvvk.c.inc | 30 +-- target/riscv/translate.c | 6 + target/riscv/vcrypto_helper.c | 63 +++---- target/riscv/vector_helper.c | 168 ++++++----------- target/riscv/vector_internals.c | 28 +++ target/riscv/vector_internals.h | 4 + 8 files changed, 186 insertions(+), 336 deletions(-)