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Tue, 9 Apr 2024 17:57:06 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7821420040; Tue, 9 Apr 2024 17:57:04 +0000 (GMT) Received: from gfwr515.rchland.ibm.com (unknown [9.10.239.103]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 9 Apr 2024 17:57:04 +0000 (GMT) From: Chalapathi V To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, fbarrat@linux.ibm.com, npiggin@gmail.com, clg@kaod.org, calebs@us.ibm.com, chalapathi.v@ibm.com, chalapathi.v@linux.ibm.com, saif.abrar@linux.vnet.ibm.com, dantan@us.ibm.com Subject: [PATCH v2 0/6] hw/ppc: SPI model Date: Tue, 9 Apr 2024 12:56:54 -0500 Message-Id: <20240409175700.27535-1-chalapathi.v@linux.ibm.com> X-Mailer: git-send-email 2.39.3 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: hgXU3BkBABf-WkbuBouoOOH2ONRbbg75 X-Proofpoint-GUID: kA5ScnOv0DyGWAmGuxUo4yif8xIp3q3q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-09_12,2024-04-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=628 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1011 mlxscore=0 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2404010000 definitions=main-2404090118 Received-SPF: pass client-ip=148.163.156.1; envelope-from=chalapathi.v@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hello, Thank You so much for reviewing patchset V1. In PATCHSET V2, removed the PNV_SPI_RESPONDER model and an existing QEMU SSI framework is used to model SPI BUS and SEEPROM model and also most of Steve's comments have been addressed. Also added the pnv-spi-seeprom qtest is added to test to check SPI traffic between SPI controller and it's attached SEEPROM device. The new qom-tree looks like below. (qemu) info qom-tree /machine (powernv10-machine) /chip[0] (power10_v2.0-pnv-chip) /pib_spic[0] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.0 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[1] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.1 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[2] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.2 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[3] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.3 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[4] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.4 (SSI) /xscom-spi-controller-regs[0] (memory-region) /pib_spic[5] (pnv-spi-controller) /bus (pnv-spi-bus) /pnv-spi-bus.5 (SSI) /xscom-spi-controller-regs[0] (memory-region) /unattached (container) /device[7] (seeprom-25csm04) /ssi-gpio-cs[0] (irq) Patches overview in V2. PATCH1: Remove SPI responder model and used SSI framework instead. PATCH2: Create a SPI controller model and implement configuration unit to model SCOM registers. Move register constants to a seperate header file pnv_spi_controller_regs.h PATCH3: SPI controller model: implement sequencer FSM and shift engine. PATCH4: Create a Microchip's SEEPROM 25csm04 model using SSI framework and move it hw/misc as it is not a power specific device. PATCH5: Connect SPI controllers to p10 chip and create keystore seeprom device of type "seeprom-25csm04" and connect cs line PIB_SPIC[2]. PATCH6: Write a qtest pnv-spi-seeprom-test to check the SPI transactions between spi controller and seeprom device. Test covered: Ran make check. Thank You, Chalapathi Chalapathi V (6): hw/ppc: remove SPI responder model hw/ppc: SPI controller model - registers implementation hw/ppc: SPI controller model - sequencer and shifter hw/misc: Microchip's 25CSM04 SEEPROM model hw/ppc: SPI controller wiring to P10 chip and create seeprom device tests/qtest: Add pnv-spi-seeprom qtest include/hw/misc/seeprom_25csm04.h | 48 + include/hw/ppc/pnv_chip.h | 3 + include/hw/ppc/pnv_spi_controller.h | 127 ++ include/hw/ppc/pnv_spi_controller_regs.h | 114 ++ include/hw/ppc/pnv_xscom.h | 3 + hw/misc/seeprom_25csm04.c | 780 +++++++++++ hw/ppc/pnv.c | 36 +- hw/ppc/pnv_spi_controller.c | 1587 ++++++++++++++++++++++ tests/qtest/pnv-spi-seeprom-test.c | 126 ++ hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/ppc/Kconfig | 2 + hw/ppc/meson.build | 1 + tests/qtest/meson.build | 1 + 14 files changed, 2831 insertions(+), 1 deletion(-) create mode 100644 include/hw/misc/seeprom_25csm04.h create mode 100644 include/hw/ppc/pnv_spi_controller.h create mode 100644 include/hw/ppc/pnv_spi_controller_regs.h create mode 100644 hw/misc/seeprom_25csm04.c create mode 100644 hw/ppc/pnv_spi_controller.c create mode 100644 tests/qtest/pnv-spi-seeprom-test.c