| Message ID | 20240422155236.129179-1-clement.mathieu--drif@eviden.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | FLTS for VT-d | expand |
Cc'ing few developers who touched the intel_iommu model ;) On 22/4/24 17:52, CLEMENT MATHIEU--DRIF wrote: > This series is the first of a list that add support for SVM in the Intel IOMMU. > > Here, we implement support for first-stage translation in VT-d. > The PASID-based IOTLB invalidation is also added in this series as it is a > requirement of FLTS. > > The last patch introduces the 'flts' option to enable the feature from > the command line. > Once enabled, several drivers of the Linux kernel use this feature. > > This work is based on the VT-d specification version 4.1 (March 2023) > > Here is a link to a GitHub repository where you can find the following elements : > - Qemu with all the patches for SVM > - ATS > - PRI > - PASID based IOTLB invalidation > - Device IOTLB invalidations > - First-stage translations > - Requests with already translated addresses > - A demo device > - A simple driver for the demo device > - A userspace program (for testing and demonstration purposes) > > https://github.com/BullSequana/Qemu-in-guest-SVM-demo > > Clément Mathieu--Drif (7): > intel_iommu: fix FRCD construction macro. > intel_iommu: rename slpte to pte before adding FLTS > intel_iommu: make types match > intel_iommu: add support for first-stage translation > intel_iommu: extract device IOTLB invalidation logic > intel_iommu: add PASID-based IOTLB invalidation > intel_iommu: add a CLI option to enable FLTS > > hw/i386/intel_iommu.c | 655 ++++++++++++++++++++++++++------- > hw/i386/intel_iommu_internal.h | 114 ++++-- > include/hw/i386/intel_iommu.h | 3 +- > 3 files changed, 609 insertions(+), 163 deletions(-) >
Hello, Adding a few people in Cc: who are familiar with the Intel IOMMU. Thanks, C. On 4/22/24 17:52, CLEMENT MATHIEU--DRIF wrote: > This series is the first of a list that add support for SVM in the Intel IOMMU. > > Here, we implement support for first-stage translation in VT-d. > The PASID-based IOTLB invalidation is also added in this series as it is a > requirement of FLTS. > > The last patch introduces the 'flts' option to enable the feature from > the command line. > Once enabled, several drivers of the Linux kernel use this feature. > > This work is based on the VT-d specification version 4.1 (March 2023) > > Here is a link to a GitHub repository where you can find the following elements : > - Qemu with all the patches for SVM > - ATS > - PRI > - PASID based IOTLB invalidation > - Device IOTLB invalidations > - First-stage translations > - Requests with already translated addresses > - A demo device > - A simple driver for the demo device > - A userspace program (for testing and demonstration purposes) > > https://github.com/BullSequana/Qemu-in-guest-SVM-demo > > Clément Mathieu--Drif (7): > intel_iommu: fix FRCD construction macro. > intel_iommu: rename slpte to pte before adding FLTS > intel_iommu: make types match > intel_iommu: add support for first-stage translation > intel_iommu: extract device IOTLB invalidation logic > intel_iommu: add PASID-based IOTLB invalidation > intel_iommu: add a CLI option to enable FLTS > > hw/i386/intel_iommu.c | 655 ++++++++++++++++++++++++++------- > hw/i386/intel_iommu_internal.h | 114 ++++-- > include/hw/i386/intel_iommu.h | 3 +- > 3 files changed, 609 insertions(+), 163 deletions(-) >
Ah, this is a duplicate effort on stage-1 translation. Hi Clement, We had ever sent a rfcv1 series "intel_iommu: Enable stage-1 translation" for both emulated and passthrough device, link: https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg02740.html which now evolves to rfcv2, link: https://github.com/yiliu1765/qemu/commits/zhenzhong/iommufd_nesting_rfcv2/ It had addressed recent community comments, also the comments in old history series: https://patchwork.kernel.org/project/kvm/cover/20210302203827.437645-1-yi.l.liu@intel.com/ Would you mind rebasing your remaining part, i.e., ATS, PRI emulation, etc on to our rfcv2? Thanks Zhenzhong >-----Original Message----- >From: Cédric Le Goater <clg@redhat.com> >Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d > >Hello, > >Adding a few people in Cc: who are familiar with the Intel IOMMU. > >Thanks, > >C. > > > > >On 4/22/24 17:52, CLEMENT MATHIEU--DRIF wrote: >> This series is the first of a list that add support for SVM in the Intel IOMMU. >> >> Here, we implement support for first-stage translation in VT-d. >> The PASID-based IOTLB invalidation is also added in this series as it is a >> requirement of FLTS. >> >> The last patch introduces the 'flts' option to enable the feature from >> the command line. >> Once enabled, several drivers of the Linux kernel use this feature. >> >> This work is based on the VT-d specification version 4.1 (March 2023) >> >> Here is a link to a GitHub repository where you can find the following >elements : >> - Qemu with all the patches for SVM >> - ATS >> - PRI >> - PASID based IOTLB invalidation >> - Device IOTLB invalidations >> - First-stage translations >> - Requests with already translated addresses >> - A demo device >> - A simple driver for the demo device >> - A userspace program (for testing and demonstration purposes) >> >> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >> >> Clément Mathieu--Drif (7): >> intel_iommu: fix FRCD construction macro. >> intel_iommu: rename slpte to pte before adding FLTS >> intel_iommu: make types match >> intel_iommu: add support for first-stage translation >> intel_iommu: extract device IOTLB invalidation logic >> intel_iommu: add PASID-based IOTLB invalidation >> intel_iommu: add a CLI option to enable FLTS >> >> hw/i386/intel_iommu.c | 655 ++++++++++++++++++++++++++------ >- >> hw/i386/intel_iommu_internal.h | 114 ++++-- >> include/hw/i386/intel_iommu.h | 3 +- >> 3 files changed, 609 insertions(+), 163 deletions(-) >>
Hi Zhenzhong, I will rebase, thanks On 01/05/2024 14:40, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > > Ah, this is a duplicate effort on stage-1 translation. > > Hi Clement, > > We had ever sent a rfcv1 series "intel_iommu: Enable stage-1 translation" > for both emulated and passthrough device, link: > https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg02740.html > which now evolves to rfcv2, link: > https://github.com/yiliu1765/qemu/commits/zhenzhong/iommufd_nesting_rfcv2/ > > It had addressed recent community comments, also the comments in old history series: > https://patchwork.kernel.org/project/kvm/cover/20210302203827.437645-1-yi.l.liu@intel.com/ > > Would you mind rebasing your remaining part, i.e., ATS, PRI emulation, etc on to our rfcv2? > > Thanks > Zhenzhong > >> -----Original Message----- >> From: Cédric Le Goater <clg@redhat.com> >> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >> >> Hello, >> >> Adding a few people in Cc: who are familiar with the Intel IOMMU. >> >> Thanks, >> >> C. >> >> >> >> >> On 4/22/24 17:52, CLEMENT MATHIEU--DRIF wrote: >>> This series is the first of a list that add support for SVM in the Intel IOMMU. >>> >>> Here, we implement support for first-stage translation in VT-d. >>> The PASID-based IOTLB invalidation is also added in this series as it is a >>> requirement of FLTS. >>> >>> The last patch introduces the 'flts' option to enable the feature from >>> the command line. >>> Once enabled, several drivers of the Linux kernel use this feature. >>> >>> This work is based on the VT-d specification version 4.1 (March 2023) >>> >>> Here is a link to a GitHub repository where you can find the following >> elements : >>> - Qemu with all the patches for SVM >>> - ATS >>> - PRI >>> - PASID based IOTLB invalidation >>> - Device IOTLB invalidations >>> - First-stage translations >>> - Requests with already translated addresses >>> - A demo device >>> - A simple driver for the demo device >>> - A userspace program (for testing and demonstration purposes) >>> >>> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >>> >>> Clément Mathieu--Drif (7): >>> intel_iommu: fix FRCD construction macro. >>> intel_iommu: rename slpte to pte before adding FLTS >>> intel_iommu: make types match >>> intel_iommu: add support for first-stage translation >>> intel_iommu: extract device IOTLB invalidation logic >>> intel_iommu: add PASID-based IOTLB invalidation >>> intel_iommu: add a CLI option to enable FLTS >>> >>> hw/i386/intel_iommu.c | 655 ++++++++++++++++++++++++++------ >> - >>> hw/i386/intel_iommu_internal.h | 114 ++++-- >>> include/hw/i386/intel_iommu.h | 3 +- >>> 3 files changed, 609 insertions(+), 163 deletions(-) >>>
Hi Clement, Sorry for late response, just back from vacation. I saw your rebased version and thanks for your work. I'll schedule a timeslot to review them. Thanks Zhenzhong >-----Original Message----- >From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d > >Hi Zhenzhong, > >I will rebase, > >thanks > >On 01/05/2024 14:40, Duan, Zhenzhong wrote: >> Caution: External email. Do not open attachments or click links, unless this >email comes from a known sender and you know the content is safe. >> >> >> Ah, this is a duplicate effort on stage-1 translation. >> >> Hi Clement, >> >> We had ever sent a rfcv1 series "intel_iommu: Enable stage-1 translation" >> for both emulated and passthrough device, link: >> https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg02740.html >> which now evolves to rfcv2, link: >> >https://github.com/yiliu1765/qemu/commits/zhenzhong/iommufd_nesting >_rfcv2/ >> >> It had addressed recent community comments, also the comments in old >history series: >> >https://patchwork.kernel.org/project/kvm/cover/20210302203827.437645 >-1-yi.l.liu@intel.com/ >> >> Would you mind rebasing your remaining part, i.e., ATS, PRI emulation, etc >on to our rfcv2? >> >> Thanks >> Zhenzhong >> >>> -----Original Message----- >>> From: Cédric Le Goater <clg@redhat.com> >>> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >>> >>> Hello, >>> >>> Adding a few people in Cc: who are familiar with the Intel IOMMU. >>> >>> Thanks, >>> >>> C. >>> >>> >>> >>> >>> On 4/22/24 17:52, CLEMENT MATHIEU--DRIF wrote: >>>> This series is the first of a list that add support for SVM in the Intel >IOMMU. >>>> >>>> Here, we implement support for first-stage translation in VT-d. >>>> The PASID-based IOTLB invalidation is also added in this series as it is a >>>> requirement of FLTS. >>>> >>>> The last patch introduces the 'flts' option to enable the feature from >>>> the command line. >>>> Once enabled, several drivers of the Linux kernel use this feature. >>>> >>>> This work is based on the VT-d specification version 4.1 (March 2023) >>>> >>>> Here is a link to a GitHub repository where you can find the following >>> elements : >>>> - Qemu with all the patches for SVM >>>> - ATS >>>> - PRI >>>> - PASID based IOTLB invalidation >>>> - Device IOTLB invalidations >>>> - First-stage translations >>>> - Requests with already translated addresses >>>> - A demo device >>>> - A simple driver for the demo device >>>> - A userspace program (for testing and demonstration purposes) >>>> >>>> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >>>> >>>> Clément Mathieu--Drif (7): >>>> intel_iommu: fix FRCD construction macro. >>>> intel_iommu: rename slpte to pte before adding FLTS >>>> intel_iommu: make types match >>>> intel_iommu: add support for first-stage translation >>>> intel_iommu: extract device IOTLB invalidation logic >>>> intel_iommu: add PASID-based IOTLB invalidation >>>> intel_iommu: add a CLI option to enable FLTS >>>> >>>> hw/i386/intel_iommu.c | 655 ++++++++++++++++++++++++++- >----- >>> - >>>> hw/i386/intel_iommu_internal.h | 114 ++++-- >>>> include/hw/i386/intel_iommu.h | 3 +- >>>> 3 files changed, 609 insertions(+), 163 deletions(-) >>>>
Hi Zhenzhong Have you had time to review the ATS series rebased on you FLTS patches? Thanks >cmd On 06/05/2024 03:38, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > > Hi Clement, > > Sorry for late response, just back from vacation. > I saw your rebased version and thanks for your work. > I'll schedule a timeslot to review them. > > Thanks > Zhenzhong > >> -----Original Message----- >> From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >> >> Hi Zhenzhong, >> >> I will rebase, >> >> thanks >> >> On 01/05/2024 14:40, Duan, Zhenzhong wrote: >>> Caution: External email. Do not open attachments or click links, unless this >> email comes from a known sender and you know the content is safe. >>> >>> Ah, this is a duplicate effort on stage-1 translation. >>> >>> Hi Clement, >>> >>> We had ever sent a rfcv1 series "intel_iommu: Enable stage-1 translation" >>> for both emulated and passthrough device, link: >>> https://lists.gnu.org/archive/html/qemu-devel/2024-01/msg02740.html >>> which now evolves to rfcv2, link: >>> >> https://github.com/yiliu1765/qemu/commits/zhenzhong/iommufd_nesting >> _rfcv2/ >>> It had addressed recent community comments, also the comments in old >> history series: >> https://patchwork.kernel.org/project/kvm/cover/20210302203827.437645 >> -1-yi.l.liu@intel.com/ >>> Would you mind rebasing your remaining part, i.e., ATS, PRI emulation, etc >> on to our rfcv2? >>> Thanks >>> Zhenzhong >>> >>>> -----Original Message----- >>>> From: Cédric Le Goater <clg@redhat.com> >>>> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >>>> >>>> Hello, >>>> >>>> Adding a few people in Cc: who are familiar with the Intel IOMMU. >>>> >>>> Thanks, >>>> >>>> C. >>>> >>>> >>>> >>>> >>>> On 4/22/24 17:52, CLEMENT MATHIEU--DRIF wrote: >>>>> This series is the first of a list that add support for SVM in the Intel >> IOMMU. >>>>> Here, we implement support for first-stage translation in VT-d. >>>>> The PASID-based IOTLB invalidation is also added in this series as it is a >>>>> requirement of FLTS. >>>>> >>>>> The last patch introduces the 'flts' option to enable the feature from >>>>> the command line. >>>>> Once enabled, several drivers of the Linux kernel use this feature. >>>>> >>>>> This work is based on the VT-d specification version 4.1 (March 2023) >>>>> >>>>> Here is a link to a GitHub repository where you can find the following >>>> elements : >>>>> - Qemu with all the patches for SVM >>>>> - ATS >>>>> - PRI >>>>> - PASID based IOTLB invalidation >>>>> - Device IOTLB invalidations >>>>> - First-stage translations >>>>> - Requests with already translated addresses >>>>> - A demo device >>>>> - A simple driver for the demo device >>>>> - A userspace program (for testing and demonstration purposes) >>>>> >>>>> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >>>>> >>>>> Clément Mathieu--Drif (7): >>>>> intel_iommu: fix FRCD construction macro. >>>>> intel_iommu: rename slpte to pte before adding FLTS >>>>> intel_iommu: make types match >>>>> intel_iommu: add support for first-stage translation >>>>> intel_iommu: extract device IOTLB invalidation logic >>>>> intel_iommu: add PASID-based IOTLB invalidation >>>>> intel_iommu: add a CLI option to enable FLTS >>>>> >>>>> hw/i386/intel_iommu.c | 655 ++++++++++++++++++++++++++- >> ----- >>>> - >>>>> hw/i386/intel_iommu_internal.h | 114 ++++-- >>>>> include/hw/i386/intel_iommu.h | 3 +- >>>>> 3 files changed, 609 insertions(+), 163 deletions(-) >>>>>
Hi Clement, I'll learn and try to give comments this week. Thanks Zhenzhong >-----Original Message----- >From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d > >Hi Zhenzhong > >Have you had time to review the ATS series rebased on you FLTS patches? > >Thanks > >cmd > > >On 06/05/2024 03:38, Duan, Zhenzhong wrote: >> Caution: External email. Do not open attachments or click links, unless this >email comes from a known sender and you know the content is safe. >> >> >> Hi Clement, >> >> Sorry for late response, just back from vacation. >> I saw your rebased version and thanks for your work. >> I'll schedule a timeslot to review them. >> >> Thanks >> Zhenzhong >> >>> -----Original Message----- >>> From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >>> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >>> >>> Hi Zhenzhong, >>> >>> I will rebase, >>> >>> thanks >>> >>> On 01/05/2024 14:40, Duan, Zhenzhong wrote: >>>> Caution: External email. Do not open attachments or click links, unless >this >>> email comes from a known sender and you know the content is safe. >>>> >>>> Ah, this is a duplicate effort on stage-1 translation. >>>> >>>> Hi Clement, >>>> >>>> We had ever sent a rfcv1 series "intel_iommu: Enable stage-1 >translation" >>>> for both emulated and passthrough device, link: >>>> https://lists.gnu.org/archive/html/qemu-devel/2024- >01/msg02740.html >>>> which now evolves to rfcv2, link: >>>> >>> >https://github.com/yiliu1765/qemu/commits/zhenzhong/iommufd_nesting >>> _rfcv2/ >>>> It had addressed recent community comments, also the comments in >old >>> history series: >>> >https://patchwork.kernel.org/project/kvm/cover/20210302203827.437645 >>> -1-yi.l.liu@intel.com/ >>>> Would you mind rebasing your remaining part, i.e., ATS, PRI emulation, >etc >>> on to our rfcv2? >>>> Thanks >>>> Zhenzhong >>>> >>>>> -----Original Message----- >>>>> From: Cédric Le Goater <clg@redhat.com> >>>>> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >>>>> >>>>> Hello, >>>>> >>>>> Adding a few people in Cc: who are familiar with the Intel IOMMU. >>>>> >>>>> Thanks, >>>>> >>>>> C. >>>>> >>>>> >>>>> >>>>> >>>>> On 4/22/24 17:52, CLEMENT MATHIEU--DRIF wrote: >>>>>> This series is the first of a list that add support for SVM in the Intel >>> IOMMU. >>>>>> Here, we implement support for first-stage translation in VT-d. >>>>>> The PASID-based IOTLB invalidation is also added in this series as it is >a >>>>>> requirement of FLTS. >>>>>> >>>>>> The last patch introduces the 'flts' option to enable the feature from >>>>>> the command line. >>>>>> Once enabled, several drivers of the Linux kernel use this feature. >>>>>> >>>>>> This work is based on the VT-d specification version 4.1 (March 2023) >>>>>> >>>>>> Here is a link to a GitHub repository where you can find the following >>>>> elements : >>>>>> - Qemu with all the patches for SVM >>>>>> - ATS >>>>>> - PRI >>>>>> - PASID based IOTLB invalidation >>>>>> - Device IOTLB invalidations >>>>>> - First-stage translations >>>>>> - Requests with already translated addresses >>>>>> - A demo device >>>>>> - A simple driver for the demo device >>>>>> - A userspace program (for testing and demonstration purposes) >>>>>> >>>>>> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >>>>>> >>>>>> Clément Mathieu--Drif (7): >>>>>> intel_iommu: fix FRCD construction macro. >>>>>> intel_iommu: rename slpte to pte before adding FLTS >>>>>> intel_iommu: make types match >>>>>> intel_iommu: add support for first-stage translation >>>>>> intel_iommu: extract device IOTLB invalidation logic >>>>>> intel_iommu: add PASID-based IOTLB invalidation >>>>>> intel_iommu: add a CLI option to enable FLTS >>>>>> >>>>>> hw/i386/intel_iommu.c | 655 >++++++++++++++++++++++++++- >>> ----- >>>>> - >>>>>> hw/i386/intel_iommu_internal.h | 114 ++++-- >>>>>> include/hw/i386/intel_iommu.h | 3 +- >>>>>> 3 files changed, 609 insertions(+), 163 deletions(-) >>>>>>
Thanks ;) >cmd On 14/05/2024 07:50, Duan, Zhenzhong wrote: > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > > Hi Clement, > > I'll learn and try to give comments this week. > > Thanks > Zhenzhong > >> -----Original Message----- >> From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >> >> Hi Zhenzhong >> >> Have you had time to review the ATS series rebased on you FLTS patches? >> >> Thanks >>> cmd >> >> On 06/05/2024 03:38, Duan, Zhenzhong wrote: >>> Caution: External email. Do not open attachments or click links, unless this >> email comes from a known sender and you know the content is safe. >>> >>> Hi Clement, >>> >>> Sorry for late response, just back from vacation. >>> I saw your rebased version and thanks for your work. >>> I'll schedule a timeslot to review them. >>> >>> Thanks >>> Zhenzhong >>> >>>> -----Original Message----- >>>> From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com> >>>> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >>>> >>>> Hi Zhenzhong, >>>> >>>> I will rebase, >>>> >>>> thanks >>>> >>>> On 01/05/2024 14:40, Duan, Zhenzhong wrote: >>>>> Caution: External email. Do not open attachments or click links, unless >> this >>>> email comes from a known sender and you know the content is safe. >>>>> Ah, this is a duplicate effort on stage-1 translation. >>>>> >>>>> Hi Clement, >>>>> >>>>> We had ever sent a rfcv1 series "intel_iommu: Enable stage-1 >> translation" >>>>> for both emulated and passthrough device, link: >>>>> https://lists.gnu.org/archive/html/qemu-devel/2024- >> 01/msg02740.html >>>>> which now evolves to rfcv2, link: >>>>> >> https://github.com/yiliu1765/qemu/commits/zhenzhong/iommufd_nesting >>>> _rfcv2/ >>>>> It had addressed recent community comments, also the comments in >> old >>>> history series: >>>> >> https://patchwork.kernel.org/project/kvm/cover/20210302203827.437645 >>>> -1-yi.l.liu@intel.com/ >>>>> Would you mind rebasing your remaining part, i.e., ATS, PRI emulation, >> etc >>>> on to our rfcv2? >>>>> Thanks >>>>> Zhenzhong >>>>> >>>>>> -----Original Message----- >>>>>> From: Cédric Le Goater <clg@redhat.com> >>>>>> Subject: Re: [PATCH intel_iommu 0/7] FLTS for VT-d >>>>>> >>>>>> Hello, >>>>>> >>>>>> Adding a few people in Cc: who are familiar with the Intel IOMMU. >>>>>> >>>>>> Thanks, >>>>>> >>>>>> C. >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> On 4/22/24 17:52, CLEMENT MATHIEU--DRIF wrote: >>>>>>> This series is the first of a list that add support for SVM in the Intel >>>> IOMMU. >>>>>>> Here, we implement support for first-stage translation in VT-d. >>>>>>> The PASID-based IOTLB invalidation is also added in this series as it is >> a >>>>>>> requirement of FLTS. >>>>>>> >>>>>>> The last patch introduces the 'flts' option to enable the feature from >>>>>>> the command line. >>>>>>> Once enabled, several drivers of the Linux kernel use this feature. >>>>>>> >>>>>>> This work is based on the VT-d specification version 4.1 (March 2023) >>>>>>> >>>>>>> Here is a link to a GitHub repository where you can find the following >>>>>> elements : >>>>>>> - Qemu with all the patches for SVM >>>>>>> - ATS >>>>>>> - PRI >>>>>>> - PASID based IOTLB invalidation >>>>>>> - Device IOTLB invalidations >>>>>>> - First-stage translations >>>>>>> - Requests with already translated addresses >>>>>>> - A demo device >>>>>>> - A simple driver for the demo device >>>>>>> - A userspace program (for testing and demonstration purposes) >>>>>>> >>>>>>> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >>>>>>> >>>>>>> Clément Mathieu--Drif (7): >>>>>>> intel_iommu: fix FRCD construction macro. >>>>>>> intel_iommu: rename slpte to pte before adding FLTS >>>>>>> intel_iommu: make types match >>>>>>> intel_iommu: add support for first-stage translation >>>>>>> intel_iommu: extract device IOTLB invalidation logic >>>>>>> intel_iommu: add PASID-based IOTLB invalidation >>>>>>> intel_iommu: add a CLI option to enable FLTS >>>>>>> >>>>>>> hw/i386/intel_iommu.c | 655 >> ++++++++++++++++++++++++++- >>>> ----- >>>>>> - >>>>>>> hw/i386/intel_iommu_internal.h | 114 ++++-- >>>>>>> include/hw/i386/intel_iommu.h | 3 +- >>>>>>> 3 files changed, 609 insertions(+), 163 deletions(-) >>>>>>>
On Mon, Apr 22, 2024 at 03:52:52PM +0000, CLEMENT MATHIEU--DRIF wrote: > This series is the first of a list that add support for SVM in the Intel IOMMU. > > Here, we implement support for first-stage translation in VT-d. > The PASID-based IOTLB invalidation is also added in this series as it is a > requirement of FLTS. > > The last patch introduces the 'flts' option to enable the feature from > the command line. > Once enabled, several drivers of the Linux kernel use this feature. > > This work is based on the VT-d specification version 4.1 (March 2023) > > Here is a link to a GitHub repository where you can find the following elements : > - Qemu with all the patches for SVM > - ATS > - PRI > - PASID based IOTLB invalidation > - Device IOTLB invalidations > - First-stage translations > - Requests with already translated addresses > - A demo device > - A simple driver for the demo device > - A userspace program (for testing and demonstration purposes) > > https://github.com/BullSequana/Qemu-in-guest-SVM-demo Pls post v2 addressing minor comments so far. > Clément Mathieu--Drif (7): > intel_iommu: fix FRCD construction macro. > intel_iommu: rename slpte to pte before adding FLTS > intel_iommu: make types match > intel_iommu: add support for first-stage translation > intel_iommu: extract device IOTLB invalidation logic > intel_iommu: add PASID-based IOTLB invalidation > intel_iommu: add a CLI option to enable FLTS > > hw/i386/intel_iommu.c | 655 ++++++++++++++++++++++++++------- > hw/i386/intel_iommu_internal.h | 114 ++++-- > include/hw/i386/intel_iommu.h | 3 +- > 3 files changed, 609 insertions(+), 163 deletions(-) > > -- > 2.44.0
On 02/06/2024 16:10, Michael S. Tsirkin wrote: > Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe. > > > On Mon, Apr 22, 2024 at 03:52:52PM +0000, CLEMENT MATHIEU--DRIF wrote: >> This series is the first of a list that add support for SVM in the Intel IOMMU. >> >> Here, we implement support for first-stage translation in VT-d. >> The PASID-based IOTLB invalidation is also added in this series as it is a >> requirement of FLTS. >> >> The last patch introduces the 'flts' option to enable the feature from >> the command line. >> Once enabled, several drivers of the Linux kernel use this feature. >> >> This work is based on the VT-d specification version 4.1 (March 2023) >> >> Here is a link to a GitHub repository where you can find the following elements : >> - Qemu with all the patches for SVM >> - ATS >> - PRI >> - PASID based IOTLB invalidation >> - Device IOTLB invalidations >> - First-stage translations >> - Requests with already translated addresses >> - A demo device >> - A simple driver for the demo device >> - A userspace program (for testing and demonstration purposes) >> >> https://github.com/BullSequana/Qemu-in-guest-SVM-demo > Pls post v2 addressing minor comments so far. Hi Michael, The comments have been addressed and I rebased my work for SVM support on Zhenzhong's FLTS implementation (who cherry picked patches from this series) You can see all the changes in my series called 'ATS support for VT-d' (posted on May 21st). I also posted the PRI series on May 30th. I'm going to post a new version of ATS today to address Philippe's comment on patch called 'make types match' Tell me if you want me to change something >cmd > >> Clément Mathieu--Drif (7): >> intel_iommu: fix FRCD construction macro. >> intel_iommu: rename slpte to pte before adding FLTS >> intel_iommu: make types match >> intel_iommu: add support for first-stage translation >> intel_iommu: extract device IOTLB invalidation logic >> intel_iommu: add PASID-based IOTLB invalidation >> intel_iommu: add a CLI option to enable FLTS >> >> hw/i386/intel_iommu.c | 655 ++++++++++++++++++++++++++------- >> hw/i386/intel_iommu_internal.h | 114 ++++-- >> include/hw/i386/intel_iommu.h | 3 +- >> 3 files changed, 609 insertions(+), 163 deletions(-) >> >> -- >> 2.44.0
This series is the first of a list that add support for SVM in the Intel IOMMU. Here, we implement support for first-stage translation in VT-d. The PASID-based IOTLB invalidation is also added in this series as it is a requirement of FLTS. The last patch introduces the 'flts' option to enable the feature from the command line. Once enabled, several drivers of the Linux kernel use this feature. This work is based on the VT-d specification version 4.1 (March 2023) Here is a link to a GitHub repository where you can find the following elements : - Qemu with all the patches for SVM - ATS - PRI - PASID based IOTLB invalidation - Device IOTLB invalidations - First-stage translations - Requests with already translated addresses - A demo device - A simple driver for the demo device - A userspace program (for testing and demonstration purposes) https://github.com/BullSequana/Qemu-in-guest-SVM-demo Clément Mathieu--Drif (7): intel_iommu: fix FRCD construction macro. intel_iommu: rename slpte to pte before adding FLTS intel_iommu: make types match intel_iommu: add support for first-stage translation intel_iommu: extract device IOTLB invalidation logic intel_iommu: add PASID-based IOTLB invalidation intel_iommu: add a CLI option to enable FLTS hw/i386/intel_iommu.c | 655 ++++++++++++++++++++++++++------- hw/i386/intel_iommu_internal.h | 114 ++++-- include/hw/i386/intel_iommu.h | 3 +- 3 files changed, 609 insertions(+), 163 deletions(-)