| Message ID | 20240503124244.8804-1-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | pci: allocate a PCI ID for RISC-V IOMMU | expand |
Hi Daniel, Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年5月3日 週五 下午8:43寫道： > > Hi, > > In this RFC I want to check with Gerd and others if it's ok to add a PCI > id for the RISC-V IOMMU device. It's currently under review in [1]. The Is the link [1] missing? Regards, Frank Chang > idea is to fold this patch into the RISC-V IOMMU series if we're all ok > with this change. > > Gerd, we picked the ID right after the PCI UFS device. Let me know if > you want another ID instead. > > > Daniel Henrique Barboza (1): > pci-ids.rst: add Red Hat pci-id for generic IOMMU device > > docs/specs/pci-ids.rst | 2 ++ > include/hw/pci/pci.h | 1 + > 2 files changed, 3 insertions(+) > > -- > 2.44.0 > >
On Fri, 3 May 2024 at 13:43, Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Hi, > > In this RFC I want to check with Gerd and others if it's ok to add a PCI > id for the RISC-V IOMMU device. It's currently under review in [1]. The > idea is to fold this patch into the RISC-V IOMMU series if we're all ok > with this change. My question here would be "why is this risc-v specific?" (and more generally "what is this for?" -- the cover letter and patch and documentation page provide almost no information about what this device is and why it needs to exist rather than using either virtio-iommu or else a model of a real hardware IOMMU.) thanks -- PMM
On Tue, May 07, 2024 at 11:37:05PM GMT, Frank Chang wrote: > Hi Daniel, > > Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年5月3日 週五 下午8:43寫道： > > > > Hi, > > > > In this RFC I want to check with Gerd and others if it's ok to add a PCI > > id for the RISC-V IOMMU device. It's currently under review in [1]. The > > Is the link [1] missing? Yes ;) Also: A bit more background on the iommu would be great, for example a pointer to the specification. take care, Gerd
On 5/7/24 12:37, Frank Chang wrote: > Hi Daniel, > > Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年5月3日 週五 下午8:43寫道： >> >> Hi, >> >> In this RFC I want to check with Gerd and others if it's ok to add a PCI >> id for the RISC-V IOMMU device. It's currently under review in [1]. The > > Is the link [1] missing? Ooops. Here's the link: [1] https://lore.kernel.org/qemu-riscv/20240307160319.675044-1-dbarboza@ventanamicro.com/ Thanks, Daniel > > Regards, > Frank Chang > >> idea is to fold this patch into the RISC-V IOMMU series if we're all ok >> with this change. >> >> Gerd, we picked the ID right after the PCI UFS device. Let me know if >> you want another ID instead. >> >> >> Daniel Henrique Barboza (1): >> pci-ids.rst: add Red Hat pci-id for generic IOMMU device >> >> docs/specs/pci-ids.rst | 2 ++ >> include/hw/pci/pci.h | 1 + >> 2 files changed, 3 insertions(+) >> >> -- >> 2.44.0 >> >>
On 5/7/24 12:53, Gerd Hoffmann wrote: > On Tue, May 07, 2024 at 11:37:05PM GMT, Frank Chang wrote: >> Hi Daniel, >> >> Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年5月3日 週五 下午8:43寫道： >>> >>> Hi, >>> >>> In this RFC I want to check with Gerd and others if it's ok to add a PCI >>> id for the RISC-V IOMMU device. It's currently under review in [1]. The >> >> Is the link [1] missing? > > Yes ;) > > Also: A bit more background on the iommu would be great, for example a > pointer to the specification. Fair enough. I'll add a pointer to the latest version of the spec: https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0 Thanks, Daniel > > take care, > Gerd >
On 5/7/24 12:44, Peter Maydell wrote: > On Fri, 3 May 2024 at 13:43, Daniel Henrique Barboza > <dbarboza@ventanamicro.com> wrote: >> >> Hi, >> >> In this RFC I want to check with Gerd and others if it's ok to add a PCI >> id for the RISC-V IOMMU device. It's currently under review in [1]. The >> idea is to fold this patch into the RISC-V IOMMU series if we're all ok >> with this change. > > My question here would be "why is this risc-v specific?" (and more > generally "what is this for?" -- the cover letter and patch and > documentation page provide almost no information about what this > device is and why it needs to exist rather than using either > virtio-iommu or else a model of a real hardware IOMMU.) The RISC-V IOMMU device emulation under review ([1]) is a reference implementation of the riscv-iommu spec [2]. AFAIK it is similar to what we already have with aarch64 'smmuv3' 'virt' bus, i.e. an impl of ARM's SMMUv3 that isn't tied to a specific vendor. The difference here is that the riscv-iommu spec, ratified by RISC-V International (RVI), predicts that the device could be implemented as a PCIe device. But RVI didn't bother assigning a PCI ID for their reference IOMMU. The existing implementation in [1] is using a Rivos PCI ID that we're treating as a placeholder only. We need an ID that reflects that this is a device that adheres to the riscv-iommu spec, not to an IOMMU of any particular vendor. Since RVI doesn't provide a PCI ID for it we went to Red Hat, and they were kind enough to give us a PCI ID for the RISC-V IOMMU reference device. I'll do a proper job this time and add all this context in the commit msg. Including a proper shout-out to Gerd and Red Hat. Thanks, Daniel [1] https://lore.kernel.org/qemu-riscv/20240307160319.675044-1-dbarboza@ventanamicro.com/ [2] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0 > > thanks > -- PMM
Hi Daniel, Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年5月8日 週三 下午8:42寫道： > > > > On 5/7/24 12:44, Peter Maydell wrote: > > On Fri, 3 May 2024 at 13:43, Daniel Henrique Barboza > > <dbarboza@ventanamicro.com> wrote: > >> > >> Hi, > >> > >> In this RFC I want to check with Gerd and others if it's ok to add a PCI > >> id for the RISC-V IOMMU device. It's currently under review in [1]. The > >> idea is to fold this patch into the RISC-V IOMMU series if we're all ok > >> with this change. > > > > My question here would be "why is this risc-v specific?" (and more > > generally "what is this for?" -- the cover letter and patch and > > documentation page provide almost no information about what this > > device is and why it needs to exist rather than using either > > virtio-iommu or else a model of a real hardware IOMMU.) > > The RISC-V IOMMU device emulation under review ([1]) is a reference implementation of > the riscv-iommu spec [2]. AFAIK it is similar to what we already have with aarch64 'smmuv3' > 'virt' bus, i.e. an impl of ARM's SMMUv3 that isn't tied to a specific vendor. > > The difference here is that the riscv-iommu spec, ratified by RISC-V International (RVI), > predicts that the device could be implemented as a PCIe device. But RVI didn't bother > assigning a PCI ID for their reference IOMMU. The existing implementation in [1] is using > a Rivos PCI ID that we're treating as a placeholder only. We need an ID that reflects that > this is a device that adheres to the riscv-iommu spec, not to an IOMMU of any particular > vendor. > > Since RVI doesn't provide a PCI ID for it we went to Red Hat, and they were kind enough > to give us a PCI ID for the RISC-V IOMMU reference device. That's great. Thanks to Red Hat. I'm wondering do we have the plan to document the new PCI ID to the IOMMU spec or somewhere else that's publicly accessible? Regards, Frank Chang > > I'll do a proper job this time and add all this context in the commit msg. Including a > proper shout-out to Gerd and Red Hat. > > > > Thanks, > > > Daniel > > > [1] https://lore.kernel.org/qemu-riscv/20240307160319.675044-1-dbarboza@ventanamicro.com/ > [2] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0 > > > > > thanks > > -- PMM >
On 5/10/24 07:47, Frank Chang wrote: > Hi Daniel, > > Daniel Henrique Barboza <dbarboza@ventanamicro.com> 於 2024年5月8日 週三 下午8:42寫道： >> >> >> >> On 5/7/24 12:44, Peter Maydell wrote: >>> On Fri, 3 May 2024 at 13:43, Daniel Henrique Barboza >>> <dbarboza@ventanamicro.com> wrote: >>>> >>>> Hi, >>>> >>>> In this RFC I want to check with Gerd and others if it's ok to add a PCI >>>> id for the RISC-V IOMMU device. It's currently under review in [1]. The >>>> idea is to fold this patch into the RISC-V IOMMU series if we're all ok >>>> with this change. >>> >>> My question here would be "why is this risc-v specific?" (and more >>> generally "what is this for?" -- the cover letter and patch and >>> documentation page provide almost no information about what this >>> device is and why it needs to exist rather than using either >>> virtio-iommu or else a model of a real hardware IOMMU.) >> >> The RISC-V IOMMU device emulation under review ([1]) is a reference implementation of >> the riscv-iommu spec [2]. AFAIK it is similar to what we already have with aarch64 'smmuv3' >> 'virt' bus, i.e. an impl of ARM's SMMUv3 that isn't tied to a specific vendor. >> >> The difference here is that the riscv-iommu spec, ratified by RISC-V International (RVI), >> predicts that the device could be implemented as a PCIe device. But RVI didn't bother >> assigning a PCI ID for their reference IOMMU. The existing implementation in [1] is using >> a Rivos PCI ID that we're treating as a placeholder only. We need an ID that reflects that >> this is a device that adheres to the riscv-iommu spec, not to an IOMMU of any particular >> vendor. >> >> Since RVI doesn't provide a PCI ID for it we went to Red Hat, and they were kind enough >> to give us a PCI ID for the RISC-V IOMMU reference device. > > That's great. Thanks to Red Hat. > I'm wondering do we have the plan to document the new PCI ID to the IOMMU spec > or somewhere else that's publicly accessible? It will be documented in QEMU, as you've already seen in this patch. I'm sure that this info will be cascaded for other databases but I'm not sure how or when. I think Gerd can give us more info about it. I guess we'll end up using this same generic ID from QEMU in the kernel side too. As of now the kernel IOMMU support is using a Rivos ID ([1], patch 3). Assuming that [1] stays this way (I'm not sure if the kernel driver is a Rivos implementation or a canonical implementation like we're doing here), we'll need to add a generic kernel support that uses the generic ID too. Thanks, Daniel [1] https://lore.kernel.org/linux-riscv/cover.1715708679.git.tjeznach@rivosinc.com/ > > Regards, > Frank Chang > >> >> I'll do a proper job this time and add all this context in the commit msg. Including a >> proper shout-out to Gerd and Red Hat. >> >> >> >> Thanks, >> >> >> Daniel >> >> >> [1] https://lore.kernel.org/qemu-riscv/20240307160319.675044-1-dbarboza@ventanamicro.com/ >> [2] https://github.com/riscv-non-isa/riscv-iommu/releases/tag/v1.0.0 >> >>> >>> thanks >>> -- PMM >>