[RESEND,v2,0/5] target/riscv: Support RISC-V privilege 1.13 spec

Message

Fea.Wang May 15, 2024, 8:05 a.m. UTC

Based on the change log for the RISC-V privilege 1.13 spec, add the
support for ss1p13.

Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72

Lists what to do without clarification or document format.
* Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip, implementation ignored)
* Added the constraint that SXLEN≥UXLEN.(Skip, implementation ignored)
* Defined the misa.V field to reflect that the V extension has been implemented.(Skip, existed) 
* Defined the RV32-only medelegh and hedelegh CSRs.(Done in these patches)
* Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension..(Skip, implementation ignored)
* Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed) 
* Defined hardware error and software check exception codes.(Done in these patches)
* Specified synchronization requirements when changing the PBMTE fields in menvcfg and henvcfg.(Skip, implementation ignored)
* Incorporated Svade and Svadu extension specifications.(Skip, existed) 


Fea.Wang (4):
  target/riscv: Support the version for ss1p13
  target/riscv: Add 'P1P13' bit in SMSTATEEN0
  target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
  target/riscv: Reserve exception codes for sw-check and hw-err

Jim Shu (1):
  target/riscv: Reuse the conversion function of priv_spec

 target/riscv/cpu.c         |  8 ++++++--
 target/riscv/cpu.h         |  5 ++++-
 target/riscv/cpu_bits.h    |  5 +++++
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/csr.c         | 39 ++++++++++++++++++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c | 17 ++++++++---------
 6 files changed, 63 insertions(+), 12 deletions(-)

Comments

Daniel Henrique Barboza May 27, 2024, 9:21 a.m. UTC | #1

Fea,

Please try to also add all RISC-V QEMU maintainers and reviewers when sending
patches. It will get your patches reviewed and queued faster. Otherwise the
maintainers can miss you your series due to high ML traffic.

You can fetch who you want to CC using the get_maintainer.pl script with the
patch files or any source file in particular, e.g.:

$ ./scripts/get_maintainer.pl -f target/riscv/cpu.c
Palmer Dabbelt <[e-mail]> (supporter:RISC-V TCG CPUs)
Alistair Francis <[e-mail]> (supporter:RISC-V TCG CPUs)
Bin Meng <[e-mail]> (supporter:RISC-V TCG CPUs)
Weiwei Li <[e-mail]> (reviewer:RISC-V TCG CPUs)
Daniel Henrique Barboza <[e-mail]> (reviewer:RISC-V TCG CPUs)
Liu Zhiwei <[e-mail]> (reviewer:RISC-V TCG CPUs)
[e-mail] (open list:RISC-V TCG CPUs)
[e-mail] (open list:All patches CC here)


I added the extra folk in the CC for this reply so don't worry about it.


Alistair, please queue this series. It's already fully acked and I would like to add
some bits on top of the priv_spec 1.13 support.


Thanks,


Daniel

On 5/15/24 05:05, Fea.Wang wrote:
> Based on the change log for the RISC-V privilege 1.13 spec, add the
> support for ss1p13.
> 
> Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72
> 
> Lists what to do without clarification or document format.
> * Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip, implementation ignored)
> * Added the constraint that SXLEN≥UXLEN.(Skip, implementation ignored)
> * Defined the misa.V field to reflect that the V extension has been implemented.(Skip, existed)
> * Defined the RV32-only medelegh and hedelegh CSRs.(Done in these patches)
> * Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension..(Skip, implementation ignored)
> * Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed)
> * Defined hardware error and software check exception codes.(Done in these patches)
> * Specified synchronization requirements when changing the PBMTE fields in menvcfg and henvcfg.(Skip, implementation ignored)
> * Incorporated Svade and Svadu extension specifications.(Skip, existed)
> 
> 
> Fea.Wang (4):
>    target/riscv: Support the version for ss1p13
>    target/riscv: Add 'P1P13' bit in SMSTATEEN0
>    target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
>    target/riscv: Reserve exception codes for sw-check and hw-err
> 
> Jim Shu (1):
>    target/riscv: Reuse the conversion function of priv_spec
> 
>   target/riscv/cpu.c         |  8 ++++++--
>   target/riscv/cpu.h         |  5 ++++-
>   target/riscv/cpu_bits.h    |  5 +++++
>   target/riscv/cpu_cfg.h     |  1 +
>   target/riscv/csr.c         | 39 ++++++++++++++++++++++++++++++++++++++
>   target/riscv/tcg/tcg-cpu.c | 17 ++++++++---------
>   6 files changed, 63 insertions(+), 12 deletions(-)
>

Fea.Wang May 30, 2024, 3:30 a.m. UTC | #2

Hi Daniel,
thank you for your help.

I found that only the cover is without many maintainers. I used to send
patches by git send-email --dry-run --to '[e-mail],
[e-mail]' --cc-cmd='scripts/get_maintainer.pl -i' patches/*.
Do you have a better script for me?
Thank you.

Sincerely,
Fea

On Mon, May 27, 2024 at 5:21 PM Daniel Henrique Barboza <
[e-mail]> wrote:

> Fea,
>
> Please try to also add all RISC-V QEMU maintainers and reviewers when
> sending
> patches. It will get your patches reviewed and queued faster. Otherwise the
> maintainers can miss you your series due to high ML traffic.
>
> You can fetch who you want to CC using the get_maintainer.pl script with
> the
> patch files or any source file in particular, e.g.:
>
> $ ./scripts/get_maintainer.pl -f target/riscv/cpu.c
> Palmer Dabbelt <[e-mail]> (supporter:RISC-V TCG CPUs)
> Alistair Francis <[e-mail]> (supporter:RISC-V TCG CPUs)
> Bin Meng <[e-mail]> (supporter:RISC-V TCG CPUs)
> Weiwei Li <[e-mail]> (reviewer:RISC-V TCG CPUs)
> Daniel Henrique Barboza <[e-mail]> (reviewer:RISC-V TCG
> CPUs)
> Liu Zhiwei <[e-mail]> (reviewer:RISC-V TCG CPUs)
> [e-mail] (open list:RISC-V TCG CPUs)
> [e-mail] (open list:All patches CC here)
>
>
> I added the extra folk in the CC for this reply so don't worry about it.
>
>
> Alistair, please queue this series. It's already fully acked and I would
> like to add
> some bits on top of the priv_spec 1.13 support.
>
>
> Thanks,
>
>
> Daniel
>
> On 5/15/24 05:05, Fea.Wang wrote:
> > Based on the change log for the RISC-V privilege 1.13 spec, add the
> > support for ss1p13.
> >
> > Ref:
> https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72
> >
> > Lists what to do without clarification or document format.
> > * Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip,
> implementation ignored)
> > * Added the constraint that SXLEN≥UXLEN.(Skip, implementation ignored)
> > * Defined the misa.V field to reflect that the V extension has been
> implemented.(Skip, existed)
> > * Defined the RV32-only medelegh and hedelegh CSRs.(Done in these
> patches)
> > * Defined the misaligned atomicity granule PMA, superseding the proposed
> Zam extension..(Skip, implementation ignored)
> > * Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed)
> > * Defined hardware error and software check exception codes.(Done in
> these patches)
> > * Specified synchronization requirements when changing the PBMTE fields
> in menvcfg and henvcfg.(Skip, implementation ignored)
> > * Incorporated Svade and Svadu extension specifications.(Skip, existed)
> >
> >
> > Fea.Wang (4):
> >    target/riscv: Support the version for ss1p13
> >    target/riscv: Add 'P1P13' bit in SMSTATEEN0
> >    target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
> >    target/riscv: Reserve exception codes for sw-check and hw-err
> >
> > Jim Shu (1):
> >    target/riscv: Reuse the conversion function of priv_spec
> >
> >   target/riscv/cpu.c         |  8 ++++++--
> >   target/riscv/cpu.h         |  5 ++++-
> >   target/riscv/cpu_bits.h    |  5 +++++
> >   target/riscv/cpu_cfg.h     |  1 +
> >   target/riscv/csr.c         | 39 ++++++++++++++++++++++++++++++++++++++
> >   target/riscv/tcg/tcg-cpu.c | 17 ++++++++---------
> >   6 files changed, 63 insertions(+), 12 deletions(-)
> >
>

Daniel Henrique Barboza May 30, 2024, 9:21 a.m. UTC | #3

Hi Fea,

On 5/30/24 00:30, Fea Wang wrote:
> Hi Daniel,
> thank you for your help.
> 
> I found that only the cover is without many maintainers. I used to send patches by git send-email --dry-run --to '[e-mail] <mailto:[e-mail]>,[e-mail] <mailto:[e-mail]>' --cc-cmd='scripts/get_maintainer.pl <http://get_maintainer.pl> -i' patches/*. Do you have a better script for me?

Hmmm no I don't actually :) my script is worse than yours. I just use a git
alias that hardcode everyone in the CC:

	askreview-riscv = send-email --suppress-cc=sob --to [e-mail] \
		--cc [e-mail] \
		--cc (everyone from the output of get_maintainers.pl for RISC-V files)

And then "git askreview-riscv (patches)"

 From reading git docs it seems like one detail with your script is that the CC
is calculated patch by patch via the "--cc-cmd" output, but the cover letter is
considered an empty commit, so the script returns nothing. This is why every
other patch has a CC but the cover doesn't.

This is more a get_maintainer.pl detail than anything, so don't worry about it.
Having the patches properly CCed is enough. We'll go after the cover-letter
manually if needed.


Thanks,

Daniel


> Thank you.
> 
> Sincerely,
> Fea
> 
> On Mon, May 27, 2024 at 5:21 PM Daniel Henrique Barboza <[e-mail] <mailto:[e-mail]>> wrote:
> 
>     Fea,
> 
>     Please try to also add all RISC-V QEMU maintainers and reviewers when sending
>     patches. It will get your patches reviewed and queued faster. Otherwise the
>     maintainers can miss you your series due to high ML traffic.
> 
>     You can fetch who you want to CC using the get_maintainer.pl <http://get_maintainer.pl> script with the
>     patch files or any source file in particular, e.g.:
> 
>     $ ./scripts/get_maintainer.pl <http://get_maintainer.pl> -f target/riscv/cpu.c
>     Palmer Dabbelt <[e-mail] <mailto:[e-mail]>> (supporter:RISC-V TCG CPUs)
>     Alistair Francis <[e-mail] <mailto:[e-mail]>> (supporter:RISC-V TCG CPUs)
>     Bin Meng <[e-mail] <mailto:[e-mail]>> (supporter:RISC-V TCG CPUs)
>     Weiwei Li <[e-mail] <mailto:[e-mail]>> (reviewer:RISC-V TCG CPUs)
>     Daniel Henrique Barboza <[e-mail] <mailto:[e-mail]>> (reviewer:RISC-V TCG CPUs)
>     Liu Zhiwei <[e-mail] <mailto:[e-mail]>> (reviewer:RISC-V TCG CPUs)
>     [e-mail] <mailto:[e-mail]> (open list:RISC-V TCG CPUs)
>     [e-mail] <mailto:[e-mail]> (open list:All patches CC here)
> 
> 
>     I added the extra folk in the CC for this reply so don't worry about it.
> 
> 
>     Alistair, please queue this series. It's already fully acked and I would like to add
>     some bits on top of the priv_spec 1.13 support.
> 
> 
>     Thanks,
> 
> 
>     Daniel
> 
>     On 5/15/24 05:05, Fea.Wang wrote:
>      > Based on the change log for the RISC-V privilege 1.13 spec, add the
>      > support for ss1p13.
>      >
>      > Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72 <https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72>
>      >
>      > Lists what to do without clarification or document format.
>      > * Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip, implementation ignored)
>      > * Added the constraint that SXLEN≥UXLEN.(Skip, implementation ignored)
>      > * Defined the misa.V field to reflect that the V extension has been implemented.(Skip, existed)
>      > * Defined the RV32-only medelegh and hedelegh CSRs.(Done in these patches)
>      > * Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension..(Skip, implementation ignored)
>      > * Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed)
>      > * Defined hardware error and software check exception codes.(Done in these patches)
>      > * Specified synchronization requirements when changing the PBMTE fields in menvcfg and henvcfg.(Skip, implementation ignored)
>      > * Incorporated Svade and Svadu extension specifications.(Skip, existed)
>      >
>      >
>      > Fea.Wang (4):
>      >    target/riscv: Support the version for ss1p13
>      >    target/riscv: Add 'P1P13' bit in SMSTATEEN0
>      >    target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
>      >    target/riscv: Reserve exception codes for sw-check and hw-err
>      >
>      > Jim Shu (1):
>      >    target/riscv: Reuse the conversion function of priv_spec
>      >
>      >   target/riscv/cpu.c         |  8 ++++++--
>      >   target/riscv/cpu.h         |  5 ++++-
>      >   target/riscv/cpu_bits.h    |  5 +++++
>      >   target/riscv/cpu_cfg.h     |  1 +
>      >   target/riscv/csr.c         | 39 ++++++++++++++++++++++++++++++++++++++
>      >   target/riscv/tcg/tcg-cpu.c | 17 ++++++++---------
>      >   6 files changed, 63 insertions(+), 12 deletions(-)
>      >
>

Andrew Jones May 30, 2024, 10:37 a.m. UTC | #4

On Thu, May 30, 2024 at 11:30:28AM GMT, Fea Wang wrote:
> Hi Daniel,
> thank you for your help.
> 
> I found that only the cover is without many maintainers. I used to send
> patches by git send-email --dry-run --to '[e-mail],
> [e-mail]' --cc-cmd='scripts/get_maintainer.pl -i' patches/*.
> Do you have a better script for me?
> Thank you.

Some maintainers frown on that because they prefer the whole series,
even if only a few patches touch code they maintain. And, the cover
letter is quite important to get the context. Also, depending on
mail client and filter configurations, CC's that are per patch can
mess up the threading, making a mess of the mailbox. I tend to
use scripts/get_maintainer.pl to pull together a set of people/lists
to CC as an independent step, dump the contents into a file and then
do 'git send-email $(cat my-series.to-list) patches/my-series'

git-publish can help with that too by capturing the "to list" and
maintaining it for you.

Thanks,
drew

> 
> Sincerely,
> Fea
> 
> On Mon, May 27, 2024 at 5:21 PM Daniel Henrique Barboza <
> [e-mail]> wrote:
> 
> > Fea,
> >
> > Please try to also add all RISC-V QEMU maintainers and reviewers when
> > sending
> > patches. It will get your patches reviewed and queued faster. Otherwise the
> > maintainers can miss you your series due to high ML traffic.
> >
> > You can fetch who you want to CC using the get_maintainer.pl script with
> > the
> > patch files or any source file in particular, e.g.:
> >
> > $ ./scripts/get_maintainer.pl -f target/riscv/cpu.c
> > Palmer Dabbelt <[e-mail]> (supporter:RISC-V TCG CPUs)
> > Alistair Francis <[e-mail]> (supporter:RISC-V TCG CPUs)
> > Bin Meng <[e-mail]> (supporter:RISC-V TCG CPUs)
> > Weiwei Li <[e-mail]> (reviewer:RISC-V TCG CPUs)
> > Daniel Henrique Barboza <[e-mail]> (reviewer:RISC-V TCG
> > CPUs)
> > Liu Zhiwei <[e-mail]> (reviewer:RISC-V TCG CPUs)
> > [e-mail] (open list:RISC-V TCG CPUs)
> > [e-mail] (open list:All patches CC here)
> >
> >
> > I added the extra folk in the CC for this reply so don't worry about it.
> >
> >
> > Alistair, please queue this series. It's already fully acked and I would
> > like to add
> > some bits on top of the priv_spec 1.13 support.
> >
> >
> > Thanks,
> >
> >
> > Daniel
> >
> > On 5/15/24 05:05, Fea.Wang wrote:
> > > Based on the change log for the RISC-V privilege 1.13 spec, add the
> > > support for ss1p13.
> > >
> > > Ref:
> > https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72
> > >
> > > Lists what to do without clarification or document format.
> > > * Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip,
> > implementation ignored)
> > > * Added the constraint that SXLEN≥UXLEN.(Skip, implementation ignored)
> > > * Defined the misa.V field to reflect that the V extension has been
> > implemented.(Skip, existed)
> > > * Defined the RV32-only medelegh and hedelegh CSRs.(Done in these
> > patches)
> > > * Defined the misaligned atomicity granule PMA, superseding the proposed
> > Zam extension..(Skip, implementation ignored)
> > > * Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed)
> > > * Defined hardware error and software check exception codes.(Done in
> > these patches)
> > > * Specified synchronization requirements when changing the PBMTE fields
> > in menvcfg and henvcfg.(Skip, implementation ignored)
> > > * Incorporated Svade and Svadu extension specifications.(Skip, existed)
> > >
> > >
> > > Fea.Wang (4):
> > >    target/riscv: Support the version for ss1p13
> > >    target/riscv: Add 'P1P13' bit in SMSTATEEN0
> > >    target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
> > >    target/riscv: Reserve exception codes for sw-check and hw-err
> > >
> > > Jim Shu (1):
> > >    target/riscv: Reuse the conversion function of priv_spec
> > >
> > >   target/riscv/cpu.c         |  8 ++++++--
> > >   target/riscv/cpu.h         |  5 ++++-
> > >   target/riscv/cpu_bits.h    |  5 +++++
> > >   target/riscv/cpu_cfg.h     |  1 +
> > >   target/riscv/csr.c         | 39 ++++++++++++++++++++++++++++++++++++++
> > >   target/riscv/tcg/tcg-cpu.c | 17 ++++++++---------
> > >   6 files changed, 63 insertions(+), 12 deletions(-)
> > >
> >

Fea.Wang June 3, 2024, 6:37 a.m. UTC | #5

Hi Daniel, Andrew:

Thank you for giving me the feedback.
I found a new command set to cc the related maintainer's email. It also
includes these emails for the cover letter.
git send-email --dry-run --to='[e-mail],[e-mail]'
--cc="$(scripts/get_maintainer.pl XXXPATCH/* |sed -e 's/$/,/')" /XXXPATCH/*

Sincerely,
Fea

On Thu, May 30, 2024 at 6:37 PM Andrew Jones <[e-mail]>
wrote:

> On Thu, May 30, 2024 at 11:30:28AM GMT, Fea Wang wrote:
> > Hi Daniel,
> > thank you for your help.
> >
> > I found that only the cover is without many maintainers. I used to send
> > patches by git send-email --dry-run --to '[e-mail],
> > [e-mail]' --cc-cmd='scripts/get_maintainer.pl -i'
> patches/*.
> > Do you have a better script for me?
> > Thank you.
>
> Some maintainers frown on that because they prefer the whole series,
> even if only a few patches touch code they maintain. And, the cover
> letter is quite important to get the context. Also, depending on
> mail client and filter configurations, CC's that are per patch can
> mess up the threading, making a mess of the mailbox. I tend to
> use scripts/get_maintainer.pl to pull together a set of people/lists
> to CC as an independent step, dump the contents into a file and then
> do 'git send-email $(cat my-series.to-list) patches/my-series'
>
> git-publish can help with that too by capturing the "to list" and
> maintaining it for you.
>
> Thanks,
> drew
>
> >
> > Sincerely,
> > Fea
> >
> > On Mon, May 27, 2024 at 5:21 PM Daniel Henrique Barboza <
> > [e-mail]> wrote:
> >
> > > Fea,
> > >
> > > Please try to also add all RISC-V QEMU maintainers and reviewers when
> > > sending
> > > patches. It will get your patches reviewed and queued faster.
> Otherwise the
> > > maintainers can miss you your series due to high ML traffic.
> > >
> > > You can fetch who you want to CC using the get_maintainer.pl script
> with
> > > the
> > > patch files or any source file in particular, e.g.:
> > >
> > > $ ./scripts/get_maintainer.pl -f target/riscv/cpu.c
> > > Palmer Dabbelt <[e-mail]> (supporter:RISC-V TCG CPUs)
> > > Alistair Francis <[e-mail]> (supporter:RISC-V TCG
> CPUs)
> > > Bin Meng <[e-mail]> (supporter:RISC-V TCG CPUs)
> > > Weiwei Li <[e-mail]> (reviewer:RISC-V TCG CPUs)
> > > Daniel Henrique Barboza <[e-mail]> (reviewer:RISC-V
> TCG
> > > CPUs)
> > > Liu Zhiwei <[e-mail]> (reviewer:RISC-V TCG CPUs)
> > > [e-mail] (open list:RISC-V TCG CPUs)
> > > [e-mail] (open list:All patches CC here)
> > >
> > >
> > > I added the extra folk in the CC for this reply so don't worry about
> it.
> > >
> > >
> > > Alistair, please queue this series. It's already fully acked and I
> would
> > > like to add
> > > some bits on top of the priv_spec 1.13 support.
> > >
> > >
> > > Thanks,
> > >
> > >
> > > Daniel
> > >
> > > On 5/15/24 05:05, Fea.Wang wrote:
> > > > Based on the change log for the RISC-V privilege 1.13 spec, add the
> > > > support for ss1p13.
> > > >
> > > > Ref:
> > >
> https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72
> > > >
> > > > Lists what to do without clarification or document format.
> > > > * Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip,
> > > implementation ignored)
> > > > * Added the constraint that SXLEN≥UXLEN.(Skip, implementation
> ignored)
> > > > * Defined the misa.V field to reflect that the V extension has been
> > > implemented.(Skip, existed)
> > > > * Defined the RV32-only medelegh and hedelegh CSRs.(Done in these
> > > patches)
> > > > * Defined the misaligned atomicity granule PMA, superseding the
> proposed
> > > Zam extension..(Skip, implementation ignored)
> > > > * Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed)
> > > > * Defined hardware error and software check exception codes.(Done in
> > > these patches)
> > > > * Specified synchronization requirements when changing the PBMTE
> fields
> > > in menvcfg and henvcfg.(Skip, implementation ignored)
> > > > * Incorporated Svade and Svadu extension specifications.(Skip,
> existed)
> > > >
> > > >
> > > > Fea.Wang (4):
> > > >    target/riscv: Support the version for ss1p13
> > > >    target/riscv: Add 'P1P13' bit in SMSTATEEN0
> > > >    target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
> > > >    target/riscv: Reserve exception codes for sw-check and hw-err
> > > >
> > > > Jim Shu (1):
> > > >    target/riscv: Reuse the conversion function of priv_spec
> > > >
> > > >   target/riscv/cpu.c         |  8 ++++++--
> > > >   target/riscv/cpu.h         |  5 ++++-
> > > >   target/riscv/cpu_bits.h    |  5 +++++
> > > >   target/riscv/cpu_cfg.h     |  1 +
> > > >   target/riscv/csr.c         | 39
> ++++++++++++++++++++++++++++++++++++++
> > > >   target/riscv/tcg/tcg-cpu.c | 17 ++++++++---------
> > > >   6 files changed, 63 insertions(+), 12 deletions(-)
> > > >
> > >
>