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[RESEND,0/6] Introduce extension implied rules

Message ID 20240605063154.31298-1-frank.chang@sifive.com (mailing list archive)
Headers show
Series Introduce extension implied rules | expand

Message

Frank Chang June 5, 2024, 6:31 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

Currently, the implied extensions are enabled and checked in
riscv_cpu_validate_set_extensions(). However, the order of enabling the
implied extensions must follow a strict sequence, which is error-prone.

This patchset introduce extension implied rule helpers to enable the
implied extensions. This also eliminates the old-fashioned ordering
requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc.,
removing the need to check the implied rules of Zvksg before Zvks.

The idea [1] and the implied rules [2] are referenced from LLVM.

[1] https://github.com/llvm/llvm-project/blob/main/llvm/lib/TargetParser/RISCVISAInfo.cpp#L875
[2] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVFeatures.td

Frank Chang (6):
  target/riscv: Introduce extension implied rules definition
  target/riscv: Introduce extension implied rule helpers
  target/riscv: Add MISA implied rules
  target/riscv: Add standard extension implied rules
  target/riscv: Add Zc extension implied rule
  target/riscv: Remove extension auto-update check statements

 target/riscv/cpu.c         | 396 +++++++++++++++++++++++++++++++++++++
 target/riscv/cpu.h         |  18 ++
 target/riscv/tcg/tcg-cpu.c | 238 +++++++++++-----------
 3 files changed, 537 insertions(+), 115 deletions(-)

--
2.43.2

Comments

Jerry Zhang Jian June 5, 2024, 7:48 a.m. UTC | #1 
Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>