Message ID | 20240606014501.20763-1-duchao@eswincomputing.com (mailing list archive) |
---|---|
Headers | show |
Series | target/riscv/kvm: QEMU support for KVM Guest Debug on RISC-V | expand |
On Thu, Jun 6, 2024 at 11:50 AM Chao Du <duchao@eswincomputing.com> wrote: > > This series implements QEMU KVM Guest Debug on RISC-V, with which we > could debug RISC-V KVM guest from the host side, using software > breakpoints. > > This series is based on riscv-to-apply.next branch and is also > available at: > https://github.com/Du-Chao/alistair23-qemu/tree/riscv-to-apply.next.0606 > > The corresponding KVM side patches have been merged already: > https://lore.kernel.org/kvm/20240402062628.5425-1-duchao@eswincomputing.com/ > > A TODO list which will be added later: > 1. HW breakpoints support > 2. A 'corner case' in which the debug exception is not inserted by the > debugger, need to be re-injected to the guest. > > v3,v4: > - rebased. > > v2->v2 resend: > - add the type conversion in patch #1 to avoid warnings > > v1->v2: > - squash patch #2 into #1 > - check the instruction length from the tail two bits, instead of passing the > length information by parameters. > > RFC->v1: > - Rebased on riscv-to-apply.next > - use configs/ definition to conditionalize debug support > > v2 link: > https://lore.kernel.org/qemu-riscv/20240528080759.26439-1-duchao@eswincomputing.com/ > v1 link: > https://lore.kernel.org/qemu-riscv/20240527021916.12953-1-duchao@eswincomputing.com/ > RFC link: > https://lore.kernel.org/qemu-riscv/20231221094923.7349-1-duchao@eswincomputing.com/ > > Chao Du (3): > target/riscv/kvm: add software breakpoints support > target/riscv/kvm: handle the exit with debug reason > target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG Thanks! Applied to riscv-to-apply.next Alistair > > configs/targets/riscv64-softmmu.mak | 1 + > target/riscv/kvm/kvm-cpu.c | 89 +++++++++++++++++++++++++++++ > 2 files changed, 90 insertions(+) > > -- > 2.17.1 >