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[00/13] target/arm: AdvSIMD conversion, part 2

Message ID 20240625050810.1475643-1-richard.henderson@linaro.org (mailing list archive)
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Series target/arm: AdvSIMD conversion, part 2 | expand

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Richard Henderson June 25, 2024, 5:07 a.m. UTC 
Convert another hand-full of instructions, plus fixes
for two issues that are related.


r~


Richard Henderson (13):
  target/arm: Fix VCMLA Dd, Dn, Dm[idx]
  target/arm: Fix SQDMULH (by element) with Q=0
  target/arm: Fix FJCVTZS vs flush-to-zero
  target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree
  target/arm: Convert SDOT, UDOT to decodetree
  target/arm: Convert SUDOT, USDOT to decodetree
  target/arm: Convert BFDOT to decodetree
  target/arm: Convert BFMLALB, BFMLALT to decodetree
  target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree
  target/arm: Add data argument to do_fp3_vector
  target/arm: Convert FCADD to decodetree
  target/arm: Convert FCMLA to decodetree
  target/arm: Delete dead code from disas_simd_indexed

 target/arm/helper.h               |  10 +
 target/arm/tcg/a64.decode         |  42 ++
 target/arm/tcg/translate-a64.c    | 811 +++++++++---------------------
 target/arm/tcg/vec_helper.c       | 100 +++-
 target/arm/vfp_helper.c           |  18 +-
 tests/tcg/aarch64/test-2375.c     |  20 +
 tests/tcg/aarch64/Makefile.target |   3 +-
 7 files changed, 422 insertions(+), 582 deletions(-)
 create mode 100644 tests/tcg/aarch64/test-2375.c