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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f9eb321d4esm79472325ad.67.2024.06.25.04.46.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jun 2024 04:46:49 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang Subject: [PATCH v3 0/6] Introduce extension implied rules Date: Tue, 25 Jun 2024 19:46:23 +0800 Message-ID: <20240625114629.27793-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x641.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Frank Chang Currently, the implied extensions are enabled and checked in riscv_cpu_validate_set_extensions(). However, the order of enabling the implied extensions must follow a strict sequence, which is error-prone. This patchset introduce extension implied rule helpers to enable the implied extensions. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc., removing the need to check the implied rules of Zvksg before Zvks. The idea [1] and the implied rules [2] are referenced from LLVM. [1] https://github.com/llvm/llvm-project/blob/main/llvm/lib/TargetParser/RISCVISAInfo.cpp#L875 [2] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVFeatures.td Changelog: v3: - Replace the enabled bitmask of type 'uint64_t' with a dynamic bitmask to support more than 64 harts. - Ensure that implied rules and hash tables are initialized/created only once. - Rename variables to align nomenclature with existing variables: - In RISCVCPUImpliedExtsRule structure: - 'implied_misas' -> 'implied_misa_exts' - 'implied_exts' -> 'implied_multi_exts' - 'misa_implied_rules' -> 'misa_ext_implied_rules' - 'ext_implied_rules' -> 'multi_ext_implied_rules' - 'riscv_misa_implied_rules' -> 'riscv_misa_ext_implied_rules' - 'riscv_ext_implied_rules -> 'riscv_multi_ext_implied_rules' v2: - Remove enabled bitmask from user-mode QEMU as there's no good way (e.g. mhartid) to distinguish the SMP cores in user-mode QEMU. - Use qatomic API to access the enabled bitmask to prevent the potential enabled bit from being cleared by another hart. Frank Chang (6): target/riscv: Introduce extension implied rules definition target/riscv: Introduce extension implied rule helpers target/riscv: Add MISA extension implied rules target/riscv: Add multi extension implied rules target/riscv: Add Zc extension implied rule target/riscv: Remove extension auto-update check statements target/riscv/cpu.c | 396 +++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 23 +++ target/riscv/tcg/tcg-cpu.c | 274 ++++++++++++++----------- 3 files changed, 574 insertions(+), 119 deletions(-) --- 2.43.2