| Message ID | 20240626-tcg-v1-0-0bad656307d8@daynix.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | tests/tcg/aarch64: Fix inline assemblies for clang | expand |
Akihiko Odaki <akihiko.odaki@daynix.com> writes: > Unlike GCC, clang checks if the operands in assembly matches with the > type in C. It also does not support "x" constraint for AArch64 and > complains about them. When are the test cases ever built with clang? Is this for Arm on Arm testing only? > > Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> > --- > Akihiko Odaki (6): > tests/tcg/arm: Fix fcvt result messages > tests/tcg/aarch64: Fix test architecture specification > tests/tcg/aarch64: Explicitly specify register width > tests/tcg/aarch64: Fix irg operand type > tests/tcg/aarch64: Do not use x constraint > tests/tcg/arm: Manually bit-cast half-precision numbers > > tests/tcg/aarch64/bti-1.c | 6 +- > tests/tcg/aarch64/bti-3.c | 6 +- > tests/tcg/aarch64/mte-1.c | 2 +- > tests/tcg/aarch64/sme-smopa-2.c | 2 +- > tests/tcg/arm/fcvt.c | 20 +- > tests/tcg/aarch64/Makefile.target | 12 +- > tests/tcg/aarch64/fcvt.ref | 604 +++++++++++++++++++------------------- > 7 files changed, 331 insertions(+), 321 deletions(-) > --- > base-commit: 74abb45dac6979e7ff76172b7f0a24e869405184 > change-id: 20240624-tcg-bf8116e80afa > > Best regards,
On 2024/06/26 23:09, Alex Bennée wrote: > Akihiko Odaki <akihiko.odaki@daynix.com> writes: > >> Unlike GCC, clang checks if the operands in assembly matches with the >> type in C. It also does not support "x" constraint for AArch64 and >> complains about them. > > When are the test cases ever built with clang? Is this for Arm on Arm > testing only? I ran test QEMU built with clang on Asahi Linux.
Unlike GCC, clang checks if the operands in assembly matches with the type in C. It also does not support "x" constraint for AArch64 and complains about them. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> --- Akihiko Odaki (6): tests/tcg/arm: Fix fcvt result messages tests/tcg/aarch64: Fix test architecture specification tests/tcg/aarch64: Explicitly specify register width tests/tcg/aarch64: Fix irg operand type tests/tcg/aarch64: Do not use x constraint tests/tcg/arm: Manually bit-cast half-precision numbers tests/tcg/aarch64/bti-1.c | 6 +- tests/tcg/aarch64/bti-3.c | 6 +- tests/tcg/aarch64/mte-1.c | 2 +- tests/tcg/aarch64/sme-smopa-2.c | 2 +- tests/tcg/arm/fcvt.c | 20 +- tests/tcg/aarch64/Makefile.target | 12 +- tests/tcg/aarch64/fcvt.ref | 604 +++++++++++++++++++------------------- 7 files changed, 331 insertions(+), 321 deletions(-) --- base-commit: 74abb45dac6979e7ff76172b7f0a24e869405184 change-id: 20240624-tcg-bf8116e80afa Best regards,