[v5,00/13] riscv: QEMU RISC-V IOMMU Support

Message

Daniel Henrique Barboza July 8, 2024, 5:34 p.m. UTC

Hi,

In this new version changes based on the suggestions made in v4 were
made.

The most notable change, however, is the merge of patches 3 (base IOMMU
emulation and 9 (s-stage and g-stage) from v4 into a single patch. There
were several instances throughout the revisions of this work where a
comment made in patch 3 was relevant or made obsolete by patch 9. Having
them merged together in a single patch will put all the translation code
in a single patch, making it easier to review the whole picture.

Series based on alistair/riscv-to-apply.next. It's also applicable on
top of master.

Patches missing acks: 3, 13.

Changes from v4:
- patch 1:
  - renamed MemTxAttrs.pasid to MemTxAttrs.pid 
- patch 2:
  - removed qemu/osdep.h include from riscv-iommu-bits.h
- patch 3:
  - squashed with patch 9 ("hw/riscv/riscv-iommu: add s-stage and g-stage support")
  - renamed 'pasid_bits' to 'pid_bits'
  - added "!s->enable_msi" check to riscv_iommu_msi_check()
  - removed riscv_iommu_msi_check() from riscv_iommu_msi_write()
- patch 13 (former 14):
  - added information on all configuration parameters in the doc
- v4 link: https://lore.kernel.org/qemu-riscv/[e-mail]/


Andrew Jones (1):
  hw/riscv/riscv-iommu: Add another irq for mrif notifications

Daniel Henrique Barboza (4):
  pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
  test/qtest: add riscv-iommu-pci tests
  qtest/riscv-iommu-test: add init queues test
  docs/specs: add riscv-iommu

Tomasz Jeznach (8):
  exec/memtxattr: add process identifier to the transaction attributes
  hw/riscv: add riscv-iommu-bits.h
  hw/riscv: add RISC-V IOMMU base emulation
  hw/riscv: add riscv-iommu-pci reference device
  hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
  hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
  hw/riscv/riscv-iommu: add ATS support
  hw/riscv/riscv-iommu: add DBG support

 docs/specs/index.rst             |    1 +
 docs/specs/pci-ids.rst           |    2 +
 docs/specs/riscv-iommu.rst       |   55 +
 docs/system/riscv/virt.rst       |   13 +
 hw/riscv/Kconfig                 |    4 +
 hw/riscv/meson.build             |    1 +
 hw/riscv/riscv-iommu-bits.h      |  417 ++++++
 hw/riscv/riscv-iommu-pci.c       |  178 +++
 hw/riscv/riscv-iommu.c           | 2370 ++++++++++++++++++++++++++++++
 hw/riscv/riscv-iommu.h           |  148 ++
 hw/riscv/trace-events            |   15 +
 hw/riscv/trace.h                 |    1 +
 hw/riscv/virt.c                  |   33 +-
 include/exec/memattrs.h          |    5 +
 include/hw/pci/pci.h             |    1 +
 include/hw/riscv/iommu.h         |   36 +
 meson.build                      |    1 +
 tests/qtest/libqos/meson.build   |    4 +
 tests/qtest/libqos/riscv-iommu.c |   76 +
 tests/qtest/libqos/riscv-iommu.h |  100 ++
 tests/qtest/meson.build          |    1 +
 tests/qtest/riscv-iommu-test.c   |  234 +++
 22 files changed, 3695 insertions(+), 1 deletion(-)
 create mode 100644 docs/specs/riscv-iommu.rst
 create mode 100644 hw/riscv/riscv-iommu-bits.h
 create mode 100644 hw/riscv/riscv-iommu-pci.c
 create mode 100644 hw/riscv/riscv-iommu.c
 create mode 100644 hw/riscv/riscv-iommu.h
 create mode 100644 hw/riscv/trace-events
 create mode 100644 hw/riscv/trace.h
 create mode 100644 include/hw/riscv/iommu.h
 create mode 100644 tests/qtest/libqos/riscv-iommu.c
 create mode 100644 tests/qtest/libqos/riscv-iommu.h
 create mode 100644 tests/qtest/riscv-iommu-test.c