[v2,00/19] ppc/pnv: Better big-core model, lpar-per-core, PC unit

Message

Nicholas Piggin July 12, 2024, 12:02 p.m. UTC

Primary motivation for this series is to improve big-core support.

This also fixes POWER8 SMT running Linux with the msgsnd fix and
setting lpar-per-core mode (which is always true on POWER8).

Since v1:
- Remove chip->pnv_machine pointer addition.
- Split cpu_pause() function into its own patch.
- Remove the _CORE_ID macro.
- Add has_lpar_per_thread machine class attribute to
  initialize the lpar mode to per-core on POWER8 machines
  instead of testing presence of machine state property.

Since rfc:
- Fixed POWER8 SMT so it doesn't have to be disabled.
- Fixed inadvertent spapr SMT bug.
- Renamed PnvCPUState.core pointer to pnv_core. (Harsh)
- Moved where it is initialised (clg)
- Avoided most qdev_get_machine() calls by adding a PnvMachineState
  pointer from PnvChip, new patch 3 (clg).
- Rename TB state to use camel case (Harsh and clg)
- Add comment to explain SPRC/SPRD is only accessed with powernv.
- Use mc->desc for error messages and avoid splitting machine init
  handlers (Harsh).
- Add max_smt_threads class attribute to avoid duplicating checks (clg)
- Rename processor_id() class method to get_pir_tir (Harsh and clg)
- Add a comment for get_pir_tir() (clg)
- Allow get_pir_tir() to be passed NULL pointers to avoid dummy
  pir/tir variables (Harsh)
- Move the PPC_CPU_HAS_CORE_SIBLINGS macros to inline functions (clg)
- Invert them (test for single-thread rather than for siblings)
  because the callers read a little better that way (Harsh).
- Propagate lpar and big-core options down to chip and core
  levels rather than having to test machine (clg)
- Significantly split the big-core patch (clg).
- Rework big-core device-tree handling to simplify it (clg).
- Make new has_smt_siblings property bool (Harsh)
- Make the big-core timebase tod quirk a machine class property
  rather than machine state (Harsh).

Thanks,
Nick

Nicholas Piggin (19):
  target/ppc: Fix msgsnd for POWER8
  ppc/pnv: Add pointer from PnvCPUState to PnvCore
  ppc/pnv: Move timebase state into PnvCore
  target/ppc: Move SPR indirect registers into PnvCore
  ppc/pnv: use class attribute to limit SMT threads for different
    machines
  ppc/pnv: Extend chip_pir class method to TIR as well
  ppc: Add a core_index to CPUPPCState for SMT vCPUs
  target/ppc: Add helpers to check for SMT sibling threads
  ppc: Add has_smt_siblings property to CPUPPCState
  ppc/pnv: Add a big-core mode that joins two regular cores
  ppc/pnv: Add allow for big-core differences in DT generation
  ppc/pnv: Implement big-core PVR for Power9/10
  ppc/pnv: Implement Power9 CPU core thread state indirect register
  ppc/pnv: Add POWER10 ChipTOD quirk for big-core
  ppc/pnv: Add big-core machine property
  system/cpus: Add cpu_pause() function
  ppc/pnv: Add a CPU nmi and resume function
  ppc/pnv: Implement POWER10 PC xscom registers for direct controls
  ppc/pnv: Add an LPAR per core machine option

 include/hw/core/cpu.h        |   8 +
 include/hw/ppc/pnv.h         |   8 +
 include/hw/ppc/pnv_chip.h    |   6 +-
 include/hw/ppc/pnv_core.h    |  31 ++++
 target/ppc/cpu.h             |  45 ++----
 hw/ppc/pnv.c                 | 305 ++++++++++++++++++++++++++++-------
 hw/ppc/pnv_chiptod.c         |   7 +-
 hw/ppc/pnv_core.c            | 125 ++++++++++++--
 hw/ppc/spapr_cpu_core.c      |  16 +-
 system/cpus.c                |  30 ++--
 target/ppc/cpu_init.c        |  26 +--
 target/ppc/excp_helper.c     |  69 ++++----
 target/ppc/misc_helper.c     | 104 ++++++------
 target/ppc/timebase_helper.c |  82 +++++-----
 14 files changed, 612 insertions(+), 250 deletions(-)