mbox series

[v8,0/8] Support RISC-V IOPMP

Message ID 20240715095702.1222213-1-ethan84@andestech.com (mailing list archive)
Headers show
Series Support RISC-V IOPMP | expand

Message

Ethan Chen July 15, 2024, 9:56 a.m. UTC 
This series implements basic functions of IOPMP specification v0.9.1 rapid-k
model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1

When IOPMP is enabled, memory access to system memory from devices and
the CPU will be checked by the IOPMP.

The issue of CPU access to non-CPU address space via IOMMU was previously
mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires
this patch.

[1] accel/tcg: Store section pointer in CPUTLBEntryFull
    https://patchew.org/QEMU/20240612081416.29704-1-jim.shu@sifive.com/20240612081416.29704-2-jim.shu@sifive.com/


Changes for v8:

  - Support transactions from CPU
  - Add an API to set up IOPMP protection for system memory
  - Add an API to configure the RISCV CPU to support IOPMP and specify the
    CPU's RRID
  - Add an API for DMA operation with IOPMP support
  - Add SPDX license identifiers to new files (Stefan W.)
  - Remove IOPMP PCI interface(pci_setup_iommu) (Zhiwei)

Changes for v7:

  - Change the specification version to v0.9.1
  - Remove the sps extension
  - Remove stall support, transaction information which need requestor device
    support.
  - Remove iopmp_cascade option for virt machine
  - Refine 'addr' range checks switch case (Daniel)

Ethan Chen (8):
  memory: Introduce memory region fetch operation
  system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
    size
  target/riscv: Add support for IOPMP
  hw/misc/riscv_iopmp: Add RISC-V IOPMP device
  hw/misc/riscv_iopmp: Add API to set up IOPMP protection for system
    memory
  hw/misc/riscv_iopmp: Add API to configure RISCV CPU IOPMP support
  hw/misc/riscv_iopmp:  Add DMA operation with IOPMP support API
  hw/riscv/virt: Add IOPMP support

 accel/tcg/cputlb.c            |   29 +-
 docs/system/riscv/virt.rst    |    5 +
 hw/misc/Kconfig               |    3 +
 hw/misc/meson.build           |    1 +
 hw/misc/riscv_iopmp.c         | 1289 +++++++++++++++++++++++++++++++++
 hw/misc/trace-events          |    3 +
 hw/riscv/Kconfig              |    1 +
 hw/riscv/virt.c               |   63 ++
 include/exec/memory.h         |   30 +
 include/hw/misc/riscv_iopmp.h |  173 +++++
 include/hw/riscv/virt.h       |    5 +-
 system/memory.c               |  104 +++
 system/physmem.c              |    4 +
 system/trace-events           |    2 +
 target/riscv/cpu_cfg.h        |    2 +
 target/riscv/cpu_helper.c     |   18 +-
 16 files changed, 1722 insertions(+), 10 deletions(-)
 create mode 100644 hw/misc/riscv_iopmp.c
 create mode 100644 include/hw/misc/riscv_iopmp.h

Comments

Daniel Henrique Barboza Nov. 5, 2024, 6:36 p.m. UTC | #1 
Hi Ethan,


Do you plan to send a new version of this work? It seems to me that we're
a couple of reviews away from getting it merged.


Thanks,

Daniel

On 7/15/24 6:56 AM, Ethan Chen wrote:
> This series implements basic functions of IOPMP specification v0.9.1 rapid-k
> model.
> The specification url:
> https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
> 
> When IOPMP is enabled, memory access to system memory from devices and
> the CPU will be checked by the IOPMP.
> 
> The issue of CPU access to non-CPU address space via IOMMU was previously
> mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires
> this patch.
> 
> [1] accel/tcg: Store section pointer in CPUTLBEntryFull
>      https://patchew.org/QEMU/20240612081416.29704-1-jim.shu@sifive.com/20240612081416.29704-2-jim.shu@sifive.com/
> 
> 
> Changes for v8:
> 
>    - Support transactions from CPU
>    - Add an API to set up IOPMP protection for system memory
>    - Add an API to configure the RISCV CPU to support IOPMP and specify the
>      CPU's RRID
>    - Add an API for DMA operation with IOPMP support
>    - Add SPDX license identifiers to new files (Stefan W.)
>    - Remove IOPMP PCI interface(pci_setup_iommu) (Zhiwei)
> 
> Changes for v7:
> 
>    - Change the specification version to v0.9.1
>    - Remove the sps extension
>    - Remove stall support, transaction information which need requestor device
>      support.
>    - Remove iopmp_cascade option for virt machine
>    - Refine 'addr' range checks switch case (Daniel)
> 
> Ethan Chen (8):
>    memory: Introduce memory region fetch operation
>    system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
>      size
>    target/riscv: Add support for IOPMP
>    hw/misc/riscv_iopmp: Add RISC-V IOPMP device
>    hw/misc/riscv_iopmp: Add API to set up IOPMP protection for system
>      memory
>    hw/misc/riscv_iopmp: Add API to configure RISCV CPU IOPMP support
>    hw/misc/riscv_iopmp:  Add DMA operation with IOPMP support API
>    hw/riscv/virt: Add IOPMP support
> 
>   accel/tcg/cputlb.c            |   29 +-
>   docs/system/riscv/virt.rst    |    5 +
>   hw/misc/Kconfig               |    3 +
>   hw/misc/meson.build           |    1 +
>   hw/misc/riscv_iopmp.c         | 1289 +++++++++++++++++++++++++++++++++
>   hw/misc/trace-events          |    3 +
>   hw/riscv/Kconfig              |    1 +
>   hw/riscv/virt.c               |   63 ++
>   include/exec/memory.h         |   30 +
>   include/hw/misc/riscv_iopmp.h |  173 +++++
>   include/hw/riscv/virt.h       |    5 +-
>   system/memory.c               |  104 +++
>   system/physmem.c              |    4 +
>   system/trace-events           |    2 +
>   target/riscv/cpu_cfg.h        |    2 +
>   target/riscv/cpu_helper.c     |   18 +-
>   16 files changed, 1722 insertions(+), 10 deletions(-)
>   create mode 100644 hw/misc/riscv_iopmp.c
>   create mode 100644 include/hw/misc/riscv_iopmp.h
>
Ethan Chen Nov. 8, 2024, 1:16 a.m. UTC | #2 
On Tue, Nov 05, 2024 at 03:36:07PM -0300, Daniel Henrique Barboza wrote:
> [EXTERNAL MAIL]
> 
> Hi Ethan,
> 
> 
> Do you plan to send a new version of this work? It seems to me that we're
> a couple of reviews away from getting it merged.
> 

Hi Daniel,

Thanks for checking in! I do plan to send an updated version, but it may take a 
bit more time.

Best regards,
Ethan

> 
> On 7/15/24 6:56 AM, Ethan Chen wrote:
> > This series implements basic functions of IOPMP specification v0.9.1 rapid-k
> > model.
> > The specification url:
> > https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1
> > 
> > When IOPMP is enabled, memory access to system memory from devices and
> > the CPU will be checked by the IOPMP.
> > 
> > The issue of CPU access to non-CPU address space via IOMMU was previously
> > mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires
> > this patch.
> > 
> > [1] accel/tcg: Store section pointer in CPUTLBEntryFull
> >      https://patchew.org/QEMU/20240612081416.29704-1-jim.shu@sifive.com/20240612081416.29704-2-jim.shu@sifive.com/
> > 
> > 
> > Changes for v8:
> > 
> >    - Support transactions from CPU
> >    - Add an API to set up IOPMP protection for system memory
> >    - Add an API to configure the RISCV CPU to support IOPMP and specify the
> >      CPU's RRID
> >    - Add an API for DMA operation with IOPMP support
> >    - Add SPDX license identifiers to new files (Stefan W.)
> >    - Remove IOPMP PCI interface(pci_setup_iommu) (Zhiwei)
> > 
> > Changes for v7:
> > 
> >    - Change the specification version to v0.9.1
> >    - Remove the sps extension
> >    - Remove stall support, transaction information which need requestor device
> >      support.
> >    - Remove iopmp_cascade option for virt machine
> >    - Refine 'addr' range checks switch case (Daniel)
> > 
> > Ethan Chen (8):
> >    memory: Introduce memory region fetch operation
> >    system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
> >      size
> >    target/riscv: Add support for IOPMP
> >    hw/misc/riscv_iopmp: Add RISC-V IOPMP device
> >    hw/misc/riscv_iopmp: Add API to set up IOPMP protection for system
> >      memory
> >    hw/misc/riscv_iopmp: Add API to configure RISCV CPU IOPMP support
> >    hw/misc/riscv_iopmp:  Add DMA operation with IOPMP support API
> >    hw/riscv/virt: Add IOPMP support
> > 
> >   accel/tcg/cputlb.c            |   29 +-
> >   docs/system/riscv/virt.rst    |    5 +
> >   hw/misc/Kconfig               |    3 +
> >   hw/misc/meson.build           |    1 +
> >   hw/misc/riscv_iopmp.c         | 1289 +++++++++++++++++++++++++++++++++
> >   hw/misc/trace-events          |    3 +
> >   hw/riscv/Kconfig              |    1 +
> >   hw/riscv/virt.c               |   63 ++
> >   include/exec/memory.h         |   30 +
> >   include/hw/misc/riscv_iopmp.h |  173 +++++
> >   include/hw/riscv/virt.h       |    5 +-
> >   system/memory.c               |  104 +++
> >   system/physmem.c              |    4 +
> >   system/trace-events           |    2 +
> >   target/riscv/cpu_cfg.h        |    2 +
> >   target/riscv/cpu_helper.c     |   18 +-
> >   16 files changed, 1722 insertions(+), 10 deletions(-)
> >   create mode 100644 hw/misc/riscv_iopmp.c
> >   create mode 100644 include/hw/misc/riscv_iopmp.h
> >