| Message ID | 20240721072422.1377506-1-alvinga@andestech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | RISC-V: Add preliminary textra trigger CSR functions | expand |
On Sun, Jul 21, 2024 at 5:26 PM Alvin Chang via <qemu-devel@nongnu.org> wrote: > > According to RISC-V Debug specification, the optional textra32 and textra64 > trigger CSRs can be used to configure additional matching conditions for the > triggers. > > This series support to write MHVALUE and MHSELECT fields into textra32 and > textra64 trigger CSRs. Besides, the additional matching condition between > textra.MHVALUE and mcontext CSR is also implemented. > > Changes from v2: > - Remove redundant log > > Changes from v1: > - Log that mhselect only supports 0 or 4 for now > - Simplify writing of tdata3 > > Alvin Chang (2): > target/riscv: Preliminary textra trigger CSR writting support > target/riscv: Add textra matching condition for the triggers Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu_bits.h | 10 +++ > target/riscv/debug.c | 132 +++++++++++++++++++++++++++++++++++++--- > target/riscv/debug.h | 3 + > 3 files changed, 138 insertions(+), 7 deletions(-) > > -- > 2.34.1 > >
Hello Alistair, > -----Original Message----- > From: Alistair Francis <alistair23@gmail.com> > Sent: Wednesday, July 24, 2024 10:40 AM > To: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> > Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org; > alistair.francis@wdc.com; bin.meng@windriver.com; liwei1518@gmail.com; > dbarboza@ventanamicro.com; zhiwei_liu@linux.alibaba.com > Subject: Re: [PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR > functions > > [EXTERNAL MAIL] > > On Sun, Jul 21, 2024 at 5:26 PM Alvin Chang via <qemu-devel@nongnu.org> > wrote: > > > > According to RISC-V Debug specification, the optional textra32 and > > textra64 trigger CSRs can be used to configure additional matching > > conditions for the triggers. > > > > This series support to write MHVALUE and MHSELECT fields into textra32 > > and > > textra64 trigger CSRs. Besides, the additional matching condition > > between textra.MHVALUE and mcontext CSR is also implemented. > > > > Changes from v2: > > - Remove redundant log > > > > Changes from v1: > > - Log that mhselect only supports 0 or 4 for now > > - Simplify writing of tdata3 > > > > Alvin Chang (2): > > target/riscv: Preliminary textra trigger CSR writting support > > target/riscv: Add textra matching condition for the triggers > > Thanks! > > Applied to riscv-to-apply.next I saw latest riscv-to-apply queue was submitted to qemu-devel yesterday. But this series was not included. Please allow me to inform this. Thanks! Best regards, Alvin Chang > > Alistair > > > > > target/riscv/cpu_bits.h | 10 +++ > > target/riscv/debug.c | 132 > +++++++++++++++++++++++++++++++++++++--- > > target/riscv/debug.h | 3 + > > 3 files changed, 138 insertions(+), 7 deletions(-) > > > > -- > > 2.34.1 > > > > CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.
On Wed, Aug 7, 2024 at 3:24 PM Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> wrote: > > Hello Alistair, > > > -----Original Message----- > > From: Alistair Francis <alistair23@gmail.com> > > Sent: Wednesday, July 24, 2024 10:40 AM > > To: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> > > Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org; > > alistair.francis@wdc.com; bin.meng@windriver.com; liwei1518@gmail.com; > > dbarboza@ventanamicro.com; zhiwei_liu@linux.alibaba.com > > Subject: Re: [PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR > > functions > > > > [EXTERNAL MAIL] > > > > On Sun, Jul 21, 2024 at 5:26 PM Alvin Chang via <qemu-devel@nongnu.org> > > wrote: > > > > > > According to RISC-V Debug specification, the optional textra32 and > > > textra64 trigger CSRs can be used to configure additional matching > > > conditions for the triggers. > > > > > > This series support to write MHVALUE and MHSELECT fields into textra32 > > > and > > > textra64 trigger CSRs. Besides, the additional matching condition > > > between textra.MHVALUE and mcontext CSR is also implemented. > > > > > > Changes from v2: > > > - Remove redundant log > > > > > > Changes from v1: > > > - Log that mhselect only supports 0 or 4 for now > > > - Simplify writing of tdata3 > > > > > > Alvin Chang (2): > > > target/riscv: Preliminary textra trigger CSR writting support > > > target/riscv: Add textra matching condition for the triggers > > > > Thanks! > > > > Applied to riscv-to-apply.next > > I saw latest riscv-to-apply queue was submitted to qemu-devel yesterday. But this series was not included. > Please allow me to inform this. Thanks! Good catch! The PR yesterday was just fixing bugs for the upcoming release [1]. As this series isn't a bug fix I dropped it from the PR. It will be in the first PR for 9.2 though 1: https://wiki.qemu.org/Planning/9.1 Alistair
> -----Original Message----- > From: Alistair Francis <alistair23@gmail.com> > Sent: Wednesday, August 7, 2024 6:59 PM > To: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> > Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org; > alistair.francis@wdc.com > Subject: Re: [PATCH v3 0/2] RISC-V: Add preliminary textra trigger CSR > functions > > [EXTERNAL MAIL] > > On Wed, Aug 7, 2024 at 3:24 PM Alvin Che-Chia Chang(張哲嘉) > <alvinga@andestech.com> wrote: > > > > Hello Alistair, > > > > > -----Original Message----- > > > From: Alistair Francis <alistair23@gmail.com> > > > Sent: Wednesday, July 24, 2024 10:40 AM > > > To: Alvin Che-Chia Chang(張哲嘉) <alvinga@andestech.com> > > > Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org; > > > alistair.francis@wdc.com; bin.meng@windriver.com; > > > liwei1518@gmail.com; dbarboza@ventanamicro.com; > > > zhiwei_liu@linux.alibaba.com > > > Subject: Re: [PATCH v3 0/2] RISC-V: Add preliminary textra trigger > > > CSR functions > > > > > > [EXTERNAL MAIL] > > > > > > On Sun, Jul 21, 2024 at 5:26 PM Alvin Chang via > > > <qemu-devel@nongnu.org> > > > wrote: > > > > > > > > According to RISC-V Debug specification, the optional textra32 and > > > > textra64 trigger CSRs can be used to configure additional matching > > > > conditions for the triggers. > > > > > > > > This series support to write MHVALUE and MHSELECT fields into > > > > textra32 and > > > > textra64 trigger CSRs. Besides, the additional matching condition > > > > between textra.MHVALUE and mcontext CSR is also implemented. > > > > > > > > Changes from v2: > > > > - Remove redundant log > > > > > > > > Changes from v1: > > > > - Log that mhselect only supports 0 or 4 for now > > > > - Simplify writing of tdata3 > > > > > > > > Alvin Chang (2): > > > > target/riscv: Preliminary textra trigger CSR writting support > > > > target/riscv: Add textra matching condition for the triggers > > > > > > Thanks! > > > > > > Applied to riscv-to-apply.next > > > > I saw latest riscv-to-apply queue was submitted to qemu-devel yesterday. But > this series was not included. > > Please allow me to inform this. Thanks! > > Good catch! > > The PR yesterday was just fixing bugs for the upcoming release [1]. > > As this series isn't a bug fix I dropped it from the PR. It will be in the first PR for > 9.2 though Got it! Thanks! Alvin Chang > > 1: https://wiki.qemu.org/Planning/9.1 > > Alistair CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally privileged information or information protected from disclosure. If you are not the intended recipient, you are hereby notified that any disclosure, copying, distribution, or use of the information contained herein is strictly prohibited. In this case, please immediately notify the sender by return e-mail, delete the message (and any accompanying documents) and destroy all printed hard copies. Thank you for your cooperation. Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.