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Mon, 22 Jul 2024 05:05:42 -0700 (PDT) Received: from avogadro.local ([151.95.101.29]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5a30a4d75acsm6060790a12.11.2024.07.22.05.05.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jul 2024 05:05:42 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 0/7] hpet: fixes for 64-bit mode and interrupt status registers Date: Mon, 22 Jul 2024 14:05:34 +0200 Message-ID: <20240722120541.70790-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.133, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The main fixes are in patches 1 and 5: - switching level->edge was not lowering the interrupt and clearing ISR - switching on the enable bit was not raising a level-triggered interrupt if the timer had fired - the timer must be kept running even if not enabled, in order to set the ISR flag, so writes to HPET_TN_CFG must not call hpet_del_timer() - 64-bit reads and writes must be implemented so that TN_SET_VAL is applied to both halves if the 64-bit counter is written with a single 8-byte write Patch 6 improves the tracking of the HPET state, by storing the full 64-bit target value of the counter (which is used to set the corresponding QEMUTimer). Patch 7 is a longstanding TODO that is enabled by all these changes, limiting the maximum timer frequency of a periodic timer. Paolo Paolo Bonzini (7): hpet: fix and cleanup persistence of interrupt status hpet: ignore high bits of comparator in 32-bit mode hpet: remove unnecessary variable "index" hpet: place read-only bits directly in "new_val" hpet: accept 64-bit reads and writes hpet: store full 64-bit target value of the counter hpet: avoid timer storms on periodic timers hw/timer/hpet.c | 329 +++++++++++++++++++----------------------- hw/timer/trace-events | 4 +- 2 files changed, 151 insertions(+), 182 deletions(-)