[v2,00/13] Add RISC-V Counter delegation ISA extension support

Message

Atish Kumar Patra July 23, 2024, 11:29 p.m. UTC

This series adds the counter delegation extension support. The counter
delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA
extensions.

1. S[m|s]csrind : The indirect CSR extension[1] which defines additional
   5 ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size limitation of
   RISC-V CSR address space.
2. Smstateen: The stateen bit[60] controls the access to the registers
   indirectly via the above indirect registers.
3. Smcdeleg/Ssccfg: The counter delegation extensions[2]

The counter delegation extension allows Supervisor mode to program the
hpmevent and hpmcounters directly without needing the assistance from the
M-mode via SBI calls. This results in a faster perf profiling and very
few traps. This extension also introduces a scountinhibit CSR which allows
to stop/start any counter directly from the S-mode. As the counter
delegation extension potentially can have more than 100 CSRs, the specificaiton
leverages the indirect CSR extension to save the precious CSR address range.

Due to the dependancy of these extensions, the following extensions must be
enabled to use the counter delegation feature in S-mode.

"smstateen=true,sscofpmf=true,ssccfg=true,smcdeleg=true,smcsrind=true,sscsrind=true"

This makes the qemu command line quite tedious. In stead of that, I tried to
enable all PMU related extensions of ssccfg is set via newly introduced
preferred rule in last 3 patches. This approach was agreed upon in previous
revision[1] as well.

The first 2 patches decouple the indirect CSR usage from AIA implementation
while patch3 adds stateen bits validation for AIA.
The PATCH4 implements indirect CSR extensions while remaining patches
implement the counter delegation extensions.

The Qemu patches can be found here:
https://github.com/atishp04/qemu/tree/b4/counter_delegation
The Linux kernel patches can be found here (WIP version due to onging upstream
dependant patches):
https://github.com/atishp04/linux/tree/b4/counter_delegation

Changes from previous RFC version:

1. Renamed sxcsrind to csrind to align with other function names.
2. Enable sscofpmf by default for virt machine.
3. Introduced a preferred extension enabling rule strategy for generic
mult-extension dependencies.
4. Enables all PMU related extensions if ssccfg extension is set. 

RFC Link:
https://lore.kernel.org/all/[e-mail]/T/

[1] https://github.com/riscv/riscv-indirect-csr-access
[2] https://github.com/riscv/riscv-smcdeleg-ssccfg

Cc: [e-mail]

Signed-off-by: Atish Patra <[e-mail]>
---
Atish Patra (7):
      target/riscv: Enable S*stateen bits for AIA
      target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg
      target/riscv: Invoke pmu init after feature enable
      target/riscv: Enable sscofpmf for bare cpu by default
      target/riscv: Repurpose the implied rule startergy
      target/riscv: Add a preferred ISA extension rule
      target/riscv: Enable PMU related extensions to preferred rule

Kaiwen Xue (6):
      target/riscv: Add properties for Indirect CSR Access extension
      target/riscv: Decouple AIA processing from xiselect and xireg
      target/riscv: Support generic CSR indirect access
      target/riscv: Add counter delegation definitions
      target/riscv: Add select value range check for counter delegation
      target/riscv: Add counter delegation/configuration support

 target/riscv/cpu.c         |  25 ++
 target/riscv/cpu.h         |  18 ++
 target/riscv/cpu_bits.h    |  34 ++-
 target/riscv/cpu_cfg.h     |   4 +
 target/riscv/csr.c         | 726 ++++++++++++++++++++++++++++++++++++++++++---
 target/riscv/machine.c     |   1 +
 target/riscv/tcg/tcg-cpu.c | 109 ++++---
 7 files changed, 845 insertions(+), 72 deletions(-)
---
base-commit: 225d5c7b671d5eaf86bf36d40e7da2d1de2cca84
change-id: 20240715-counter_delegation-10ab44c7d2c0
--
Regards,
Atish patra