mbox series

[v3,0/4] Add support for Zhaoxin Yongfeng CPU model and

Message ID 20240809094259.119221-1-ewanhai-oc@zhaoxin.com (mailing list archive)
Headers show
Series Add support for Zhaoxin Yongfeng CPU model and | expand

Message

EwanHai Aug. 9, 2024, 9:42 a.m. UTC 
This patch series introduces support for the Zhaoxin Yongfeng CPU model and
includes improvements and updates specific to Zhaoxin CPUs (including vendor
"Centaurhauls" and "Shanghai"). The changes ensure that QEMU can correctly
identify and emulate Zhaoxin CPUs, accurately reflecting their functionality
and performance characteristics.

### Summary of changes
EwanHai (4):
  target/i386: Add support for Zhaoxin CPU vendor identification
  target/i386: Add CPUID leaf 0xC000_0001 EDX definitions
  target/i386: Introduce Zhaoxin Yongfeng CPU model
  target/i386: Mask CMPLegacy bit in CPUID[0x80000001].ECX for Zhaoxin
    CPUs

 target/i386/cpu.c | 131 ++++++++++++++++++++++++++++++++++++++++++++--
 target/i386/cpu.h |  41 ++++++++++++++-
 2 files changed, 167 insertions(+), 5 deletions(-)

v3 -> v2:
1. Added a more detailed description of the CPUID[0x80000001].ECX.CMPLegacy
bit masking.

v2 link:
https://lore.kernel.org/all/20240704112511.184257-1-ewanhai-oc@zhaoxin.com/


v2 -> v1:
1. Removed VIA-related information from the patch description to avoid
misunderstanding.
2. Replaced CPUID_VENDOR_VIA with CPUID_VENDOR_ZHAOXIN1 because the
"Centaurhauls" vendor ID now belongs to Zhaoxin.The previous CPUID_VENDOR_VIA
macro was only defined but never used in QEMU, making this change
straightforward.

v1 link:
https://lore.kernel.org/qemu-devel/20240625091905.1325205-1-ewanhai-
oc@zhaoxin.com/

### Known Issues
1. Issue with VMX Preemption Timer Rate on Yongfeng CPU:
   - Description: On Yongfeng CPUs, the VMX preemption timer rate is 128,
     meaning that bits 4:0 of MSR_IA32_VMX_MISC_CTLS should be set to 7.
     However, due to Intel's rate being 5, the Linux kernel has hardcoded
     this value as 5: `#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5`.
   - Impact: This discrepancy can cause incorrect behavior in the VMX
     preemption timer on Yongfeng CPUs.
   - Workaround: A patch to correct this issue in the Linux kernel is
     currently being prepared and will be submitted soon.