[v4,0/2] riscv: char: Avoid dropped charecters

Message

Alistair Francis Sept. 10, 2024, 4:54 a.m. UTC

This series fixes: https://gitlab.com/qemu-project/qemu/-/issues/2114

This converts the RISC-V charecter device callers of qemu_chr_fe_write()
to either use qemu_chr_fe_write_all() or to call qemu_chr_fe_write() async
and act on the return value.

v4:
 - Drop the unused char_tx_time
 - Update the migration in vmstate_sifive_uart
v3:
 - Fixup spelling
v2:
 - Use Fifo8 for the Sifive UART instead of a custom FIFO

Alistair Francis (2):
  hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all
  hw/char: sifive_uart: Print uart characters async

 include/hw/char/sifive_uart.h | 16 +++++-
 hw/char/riscv_htif.c          | 12 ++++-
 hw/char/sifive_uart.c         | 94 ++++++++++++++++++++++++++++++++---
 3 files changed, 112 insertions(+), 10 deletions(-)

Comments

Thomas Huth Oct. 17, 2024, 1:22 p.m. UTC | #1

On 10/09/2024 06.54, Alistair Francis wrote:
> This series fixes: https://gitlab.com/qemu-project/qemu/-/issues/2114
> 
> This converts the RISC-V charecter device callers of qemu_chr_fe_write()
> to either use qemu_chr_fe_write_all() or to call qemu_chr_fe_write() async
> and act on the return value.
> 
> v4:
>   - Drop the unused char_tx_time
>   - Update the migration in vmstate_sifive_uart
> v3:
>   - Fixup spelling
> v2:
>   - Use Fifo8 for the Sifive UART instead of a custom FIFO
> 
> Alistair Francis (2):
>    hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all
>    hw/char: sifive_uart: Print uart characters async

  Hi!

What's the status of these patches? Are they good to go, or do they still 
need more work? (I'm asking because I'd like to convert 
tests/avocado/riscv_opensbi.py to the functional test framework, but it 
would be good to have the problem with the dropped characters fixed first)

  Thanks,
   Thomas

Alistair Francis Oct. 21, 2024, 3:44 a.m. UTC | #2

On Thu, Oct 17, 2024 at 11:22 PM Thomas Huth <[e-mail]> wrote:
>
> On 10/09/2024 06.54, Alistair Francis wrote:
> > This series fixes: https://gitlab.com/qemu-project/qemu/-/issues/2114
> >
> > This converts the RISC-V charecter device callers of qemu_chr_fe_write()
> > to either use qemu_chr_fe_write_all() or to call qemu_chr_fe_write() async
> > and act on the return value.
> >
> > v4:
> >   - Drop the unused char_tx_time
> >   - Update the migration in vmstate_sifive_uart
> > v3:
> >   - Fixup spelling
> > v2:
> >   - Use Fifo8 for the Sifive UART instead of a custom FIFO
> >
> > Alistair Francis (2):
> >    hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all
> >    hw/char: sifive_uart: Print uart characters async
>
>   Hi!
>
> What's the status of these patches? Are they good to go, or do they still
> need more work? (I'm asking because I'd like to convert
> tests/avocado/riscv_opensbi.py to the functional test framework, but it
> would be good to have the problem with the dropped characters fixed first)

I think they are good to go

Applied to riscv-to-apply.next

Alistair

>
>   Thanks,
>    Thomas
>