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[v9,00/12] riscv: QEMU RISC-V IOMMU Support

Message ID 20241004155721.2154626-1-dbarboza@ventanamicro.com (mailing list archive)
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Series riscv: QEMU RISC-V IOMMU Support | expand

Message

Daniel Henrique Barboza Oct. 4, 2024, 3:57 p.m. UTC 
Hi,

In this new version we fixed the IOVA == GPA MSI early check in patch 3,
in riscv_iommu_spa_fetch(), after discussions with Tomasz and Drew on
v8.

The motivation behind what was being was making the emulation work with
the existing VFIO irqbypass support in the kernel. In the end this was
not a valid design choice - we were not following what the riscv-iommu
spec dictates when dealing with the IOVA==GPA case. To support
VFIO+irqbypass for the riscv-iommu spec 1.0 the Linux kernel will need
to do extra work [1].

No other changes made. Patches based on master. All patches acked.

Changes from v8:
- patch 3:
  - add the "!en_s" condition when checking for IOVA == GPA in
    riscv_iommu_spa_fetch()
- v8 link: https://lore.kernel.org/qemu-riscv/20241002010314.1928515-1-dbarboza@ventanamicro.com

[1] https://lore.kernel.org/qemu-riscv/CAH2o1u6h5nOMuGq8opXQNm6M=D=TrvygmoS+hHwmrgViy3reFA@mail.gmail.com/


Daniel Henrique Barboza (4):
  pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device
  test/qtest: add riscv-iommu-pci tests
  qtest/riscv-iommu-test: add init queues test
  docs/specs: add riscv-iommu

Tomasz Jeznach (8):
  exec/memtxattr: add process identifier to the transaction attributes
  hw/riscv: add riscv-iommu-bits.h
  hw/riscv: add RISC-V IOMMU base emulation
  hw/riscv: add riscv-iommu-pci reference device
  hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug
  hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)
  hw/riscv/riscv-iommu: add ATS support
  hw/riscv/riscv-iommu: add DBG support

 docs/specs/index.rst             |    1 +
 docs/specs/pci-ids.rst           |    2 +
 docs/specs/riscv-iommu.rst       |   90 ++
 docs/system/riscv/virt.rst       |   13 +
 hw/riscv/Kconfig                 |    4 +
 hw/riscv/meson.build             |    1 +
 hw/riscv/riscv-iommu-bits.h      |  421 ++++++
 hw/riscv/riscv-iommu-pci.c       |  202 +++
 hw/riscv/riscv-iommu.c           | 2399 ++++++++++++++++++++++++++++++
 hw/riscv/riscv-iommu.h           |  130 ++
 hw/riscv/trace-events            |   17 +
 hw/riscv/trace.h                 |    1 +
 hw/riscv/virt.c                  |   33 +-
 include/exec/memattrs.h          |    5 +
 include/hw/pci/pci.h             |    1 +
 include/hw/riscv/iommu.h         |   36 +
 meson.build                      |    1 +
 tests/qtest/libqos/meson.build   |    4 +
 tests/qtest/libqos/riscv-iommu.c |   76 +
 tests/qtest/libqos/riscv-iommu.h |  101 ++
 tests/qtest/meson.build          |    1 +
 tests/qtest/riscv-iommu-test.c   |  210 +++
 22 files changed, 3748 insertions(+), 1 deletion(-)
 create mode 100644 docs/specs/riscv-iommu.rst
 create mode 100644 hw/riscv/riscv-iommu-bits.h
 create mode 100644 hw/riscv/riscv-iommu-pci.c
 create mode 100644 hw/riscv/riscv-iommu.c
 create mode 100644 hw/riscv/riscv-iommu.h
 create mode 100644 hw/riscv/trace-events
 create mode 100644 hw/riscv/trace.h
 create mode 100644 include/hw/riscv/iommu.h
 create mode 100644 tests/qtest/libqos/riscv-iommu.c
 create mode 100644 tests/qtest/libqos/riscv-iommu.h
 create mode 100644 tests/qtest/riscv-iommu-test.c