| Message ID | 20241029091729.3317512-1-jamin_lin@aspeedtech.com (mailing list archive) |
|---|---|
| Headers | show
Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B718D2AB01 for <qemu-devel@archiver.kernel.org>; Tue, 29 Oct 2024 09:18:34 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from <qemu-devel-bounces@nongnu.org>) id 1t5iMB-0000WO-OY; Tue, 29 Oct 2024 05:17:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <jamin_lin@aspeedtech.com>) id 1t5iM8-0000V9-Ff; Tue, 29 Oct 2024 05:17:40 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <jamin_lin@aspeedtech.com>) id 1t5iM6-0003A3-Au; Tue, 29 Oct 2024 05:17:40 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 29 Oct 2024 17:17:29 +0800 Received: from localhost.localdomain (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 29 Oct 2024 17:17:29 +0800 To: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Steven Lee <steven_lee@aspeedtech.com>, Troy Lee <leetroy@gmail.com>, Andrew Jeffery <andrew@codeconstruct.com.au>, "Joel Stanley" <joel@jms.id.au>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>, Bin Meng <bmeng.cn@gmail.com>, "open list:ASPEED BMCs" <qemu-arm@nongnu.org>, "open list:All patches CC here" <qemu-devel@nongnu.org>, "open list:SD (Secure Card)" <qemu-block@nongnu.org> CC: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>, <yunlin.tang@aspeedtech.com> Subject: [PATCH v1 0/8] Support RTC for AST2700 Date: Tue, 29 Oct 2024 17:17:21 +0800 Message-ID: <20241029091729.3317512-1-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Reply-to: Jamin Lin <jamin_lin@aspeedtech.com> From: Jamin Lin via <qemu-devel@nongnu.org> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org |
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Support RTC for AST2700
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change from v1: 1. Support RTC for AST2700. 2. Support SDHCI write protected pin inverted for AST2500 and AST2600. 3. Introduce Capabilities Register 2 for SD slot 0 and 1. 4. Support create flash devices via command line for AST1030. Jamin Lin (8): aspeed/soc: Support RTC for AST2700 hw/timer/aspeed: Fix coding style hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600 hw/sd/sdhci: Fix coding style hw/sd/sdhci: Introduce a new Write Protected pin inverted property hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1 hw/arm/aspeed: Invert sdhci write protected pin for AST2600 and AST2500 EVBs aspeed: Support create flash devices via command line for AST1030 hw/arm/aspeed.c | 30 ++++++++++++------ hw/arm/aspeed_ast27x0.c | 11 +++++++ hw/sd/aspeed_sdhci.c | 40 ++++++++++++++++------- hw/sd/sdhci.c | 70 ++++++++++++++++++++++++++++------------- hw/timer/aspeed_timer.c | 15 +++++---- include/hw/arm/aspeed.h | 1 + include/hw/sd/sdhci.h | 5 +++ 7 files changed, 123 insertions(+), 49 deletions(-)