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[RFC,v4,0/2] target/riscv: add wrapper for target specific macros in atomicity check.

Message ID 20241029194348.59574-1-paolo.savini@embecosm.com (mailing list archive)
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Series target/riscv: add wrapper for target specific macros in atomicity check. | expand

Message

Paolo Savini Oct. 29, 2024, 7:43 p.m. UTC 
The version 4 of the patch wraps the host specific macros used to check
the support for atomic 128 bit memory operations into generic macros.
The patch also adjusts the indentation of the if/else clauses and the comment
about the above mentioned check for atomic 128b load/store to reflect better the
code.

Changes from V3:
- patch 2:
  - add generic wrapper macro to flag host 128b atomic mem op support.
  - fix if-else indentation.
  - improve comment about the checks for host atomic 128b mem op support.

Previous versions:
- v1: https://lore.kernel.org/all/20240717153040.11073-1-paolo.savini@embecosm.com/
- v2: https://lore.kernel.org/all/20241002135708.99146-1-paolo.savini@embecosm.com/
- v3: https://lore.kernel.org/all/20241014220153.196183-1-paolo.savini@embecosm.com/

Cc: Richard Handerson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Weiwei Li <liwei1518@gmail.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Helene Chelin <helene.chelin@embecosm.com>
Cc: Nathan Egge <negge@google.com>
Cc: Max Chou <max.chou@sifive.com>

Helene CHELIN (1):
  target/riscv: rvv: reduce the overhead for simple RISC-V vector
    unit-stride loads and stores

Paolo Savini (1):
  target/riscv: rvv: improve performance of RISC-V vector loads and
    stores on large amounts of data.

 target/riscv/vector_helper.c    | 64 ++++++++++++++++++++++++++++++++-
 target/riscv/vector_internals.h | 12 +++++++
 2 files changed, 75 insertions(+), 1 deletion(-)