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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-724078a9058sm2900715b3a.77.2024.11.07.23.05.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Nov 2024 23:05:02 -0800 (PST) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jim Shu Subject: [PATCH v3 0/3] Support 64-bit address of initrd Date: Fri, 8 Nov 2024 15:04:51 +0800 Message-Id: <20241108070454.12699-1-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=jim.shu@sifive.com; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Support to load DTB after 3GB on RV64 system, so that larger initrd doesn't be overlapped to DTB. DTB loading now will check if overlapping to kernel/initrd and report this error. Verify the patch via running 4GB initramfs on the virt machine. Changes for v3: - Change struct RISCVBootInfo from machine state to local variables. Changes for v2: - Add DTB overlapping checking and struct RISCVBootInfo - Remove the commit to change #address-cell of 'initrd-[start|end]' Jim Shu (3): hw/riscv: Support to load DTB after 3GB memory on 64-bit system. hw/riscv: Add a new struct RISCVBootInfo hw/riscv: Add the checking if DTB overlaps to kernel or initrd hw/riscv/boot.c | 94 +++++++++++++++++++++--------- hw/riscv/microchip_pfsoc.c | 14 +++-- hw/riscv/opentitan.c | 5 +- hw/riscv/sifive_e.c | 5 +- hw/riscv/sifive_u.c | 15 ++--- hw/riscv/spike.c | 15 ++--- hw/riscv/virt.c | 14 +++-- include/hw/riscv/boot.h | 28 ++++++--- include/hw/riscv/microchip_pfsoc.h | 1 + include/hw/riscv/opentitan.h | 1 + include/hw/riscv/sifive_e.h | 1 + include/hw/riscv/sifive_u.h | 1 + include/hw/riscv/spike.h | 1 + include/hw/riscv/virt.h | 1 + 14 files changed, 130 insertions(+), 66 deletions(-)