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[124.171.217.17]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-7f41f48d32bsm3110444a12.17.2024.11.08.07.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Nov 2024 07:42:37 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , "Michael S. Tsirkin" , Marcel Apfelbaum , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Gerd Hoffmann Subject: [RFC PATCH 0/5] Add XHCI TR NOOP support, plus PCI, MSIX changes Date: Sat, 9 Nov 2024 01:42:23 +1000 Message-ID: <20241108154229.263097-1-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This RFC is wide-ranging for such a simple addition of XHCI TR NOOP command, because adding qtests for it caught up some PCI/MSIX issues. Firstly, the XHCI host shares a BAR between device registers and MSIX space, which is not handled by qtest/pci. Keeping track of BAR mappings in qtest and allowing MSIX to use an existing mapping seems to work. For XHCI qtest, I added a MSIX check to ensure interrupts are working correctly. As part of that I need to dequeue masked interrupts which seems to require PBA writes to clear them, but I could be way off base here. Adding that does cause e1000e qtest to break, because it doesn't like clear pending via PBA. The XHCI model change gets AIX's XHCI driver working, so that's another data point beyond the simple qtest for it added here. Unfortunately it is not so easy to independently test. Any guidance or input would be welcome. Thanks, Nick Nicholas Piggin (5): qtest/pci: Enforce balanced iomap/unmap qtest/libqos/pci: Fix msix_enable sharing bar0 pci/msix: Implement PBA writes qtest/xhci: Add controller and device setup and ring tests hw/usb: Support XHCI TR NOOP commands tests/qtest/libqos/ahci.h | 1 + tests/qtest/libqos/pci.h | 4 + tests/qtest/libqos/virtio-pci.h | 1 + tests/qtest/usb-hcd-xhci-test.h | 232 ++++++++++++++ hw/pci/msix.c | 16 + hw/usb/hcd-xhci.c | 28 +- tests/qtest/ahci-test.c | 2 + tests/qtest/libqos/ahci.c | 6 + tests/qtest/libqos/pci.c | 75 ++++- tests/qtest/libqos/virtio-pci.c | 6 +- tests/qtest/usb-hcd-xhci-test.c | 540 +++++++++++++++++++++++++++++++- 11 files changed, 893 insertions(+), 18 deletions(-) create mode 100644 tests/qtest/usb-hcd-xhci-test.h