mbox series

[v3,0/4] Improve Mips target

Message ID 20241112164130.2396737-1-aleksandar.rakic@htecgroup.com (mailing list archive)
Headers show
Series Improve Mips target | expand

Message

Aleksandar Rakic Nov. 12, 2024, 4:41 p.m. UTC
This patch series adds support for emulation of CRC32 instructions for
the Mips target in QEMU, skips NaN mode check for soft-float, adds a CLI
flag for enabling an MSA feature, and enables the MSA for
MIPS64R2-generic.

There aren't tests for these improvements.

The patch 1/8 "Add CP0 MemoryMapID register implementation" from v2 has
been dropped from v3 since it has been accepted and integrated into the
master branch.

The patch 3/8 "GTM19-448: Fix script to work without realpath" from v2
will be sent separately as it is a fix to a general bug and is intended
for other maintainers.

The patch 5/8 "Add micromips to P5600" from v2 has been dropped from v3
since the latest document for P5600 with eventually updated field
CP0_Config3_ISA that would support microMIPS hasn't been found.

The patch 6/8 "Revert use of clock_gettime for benchmarking" from v2 has
been dropped from v3 because it seems that clock_gettime and
CLOCK_MONOTONIC exist in MinGW headers and that QEMU builds with MinGW.

The patch 7/8 "target/mips: Enable MSA ASE for mips32r6-generic" from v2
has been dropped from v3 since it has been accepted and integrated into
the master branch.

When it comes to the patch 8/8 "target/mips: Enable MSA ASE for
mips64R2-generic" from v2, the cpu Loongson-3A4000 supports both
mips64r2 and the MSA, so I'm not sure whether to drop this patch.

Regarding the DSPRAM for I6500, I heard that the IP for the DSPRAM for
mips64r6 hasn't been published, but in the document "MIPS64® I6500
Multiprocessing System Programmer’s Guide" the DSPRAM is elaborated, so
I don't know whether to add support for the DSPRAM.

Most of the following patches are cherry-picked from the branch
mips_rel/4_1_0/master on the MIPS' repository:
https://github.com/MIPS/gnutools-qemu/
Further details on individual changes are included in the respective
patches. An instance of a pipeline of QEMU CI jobs run with input
variable QEMU_CI=1 for this patch series is available here:
https://gitlab.com/rakicaleksandar1999/qemu/-/pipelines/1533819034
and for the master branch is available here:
https://gitlab.com/rakicaleksandar1999/qemu/-/pipelines/1533465414

We are open for a discussion.

Comments

Aleksandar Rakic Nov. 12, 2024, 4:41 p.m. UTC | #1
Aleksandar Rakic (4):
  Add support for emulation of CRC32 instructions
  Skip NaN mode check for soft-float
  target/mips: Enable MSA ASE using a CLI flag
  target/mips: Enable MSA ASE for mips64R2-generic

 linux-user/mips/cpu_loop.c       |  6 ++++--
 target/mips/cpu-defs.c.inc       |  4 +++-
 target/mips/cpu.c                | 16 ++++++++++++++++
 target/mips/cpu.h                |  1 +
 target/mips/helper.h             |  2 ++
 target/mips/internal.h           |  2 +-
 target/mips/meson.build          |  1 +
 target/mips/tcg/op_helper.c      | 26 ++++++++++++++++++++++++++
 target/mips/tcg/rel6.decode      |  5 +++++
 target/mips/tcg/rel6_translate.c | 14 ++++++++++++++
 target/mips/tcg/translate.c      | 25 +++++++++++++++++++++++++
 target/mips/tcg/translate.h      |  3 +++
 12 files changed, 101 insertions(+), 4 deletions(-)