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([193.104.68.137]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5cf03c8130dsm6137004a12.88.2024.11.12.08.42.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 08:42:23 -0800 (PST) From: Aleksandar Rakic X-Google-Original-From: Aleksandar Rakic To: qemu-devel@nongnu.org Cc: aleksandar.rakic@htecgroup.com, djordje.todorovic@htecgroup.com, cfu@mips.com, arikalo@gmail.com, peter.maydell@linaro.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, kwolf@redhat.com, hreitz@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, pierrick.bouvier@linaro.org, berrange@redhat.com Subject: [PATCH v3 0/4] Improve Mips target Date: Tue, 12 Nov 2024 17:41:25 +0100 Message-Id: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=rakicaleksandar1999@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 12 Nov 2024 12:37:37 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patch series adds support for emulation of CRC32 instructions for the Mips target in QEMU, skips NaN mode check for soft-float, adds a CLI flag for enabling an MSA feature, and enables the MSA for MIPS64R2-generic. There aren't tests for these improvements. The patch 1/8 "Add CP0 MemoryMapID register implementation" from v2 has been dropped from v3 since it has been accepted and integrated into the master branch. The patch 3/8 "GTM19-448: Fix script to work without realpath" from v2 will be sent separately as it is a fix to a general bug and is intended for other maintainers. The patch 5/8 "Add micromips to P5600" from v2 has been dropped from v3 since the latest document for P5600 with eventually updated field CP0_Config3_ISA that would support microMIPS hasn't been found. The patch 6/8 "Revert use of clock_gettime for benchmarking" from v2 has been dropped from v3 because it seems that clock_gettime and CLOCK_MONOTONIC exist in MinGW headers and that QEMU builds with MinGW. The patch 7/8 "target/mips: Enable MSA ASE for mips32r6-generic" from v2 has been dropped from v3 since it has been accepted and integrated into the master branch. When it comes to the patch 8/8 "target/mips: Enable MSA ASE for mips64R2-generic" from v2, the cpu Loongson-3A4000 supports both mips64r2 and the MSA, so I'm not sure whether to drop this patch. Regarding the DSPRAM for I6500, I heard that the IP for the DSPRAM for mips64r6 hasn't been published, but in the document "MIPS64® I6500 Multiprocessing System Programmer’s Guide" the DSPRAM is elaborated, so I don't know whether to add support for the DSPRAM. Most of the following patches are cherry-picked from the branch mips_rel/4_1_0/master on the MIPS' repository: https://github.com/MIPS/gnutools-qemu/ Further details on individual changes are included in the respective patches. An instance of a pipeline of QEMU CI jobs run with input variable QEMU_CI=1 for this patch series is available here: https://gitlab.com/rakicaleksandar1999/qemu/-/pipelines/1533819034 and for the master branch is available here: https://gitlab.com/rakicaleksandar1999/qemu/-/pipelines/1533465414 We are open for a discussion.