[v4,0/6] Introduce svukte ISA extension

Message

Fea.Wang Nov. 20, 2024, 7:48 a.m. UTC

The Svukte ISA extension has been approved for fast-track development.
https://lf-riscv.atlassian.net/browse/RVS-2977 
And there are Linux patches for the Svukte that are under review.
https://lore.kernel.org/kvm/[e-mail]/T/#mf70fcb22cd2987ad268c0efee9b8583197d3cb4f

Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.

Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564

base-commit: 27652f9ca9d831c67dd447346c6ee953669255f0

[v4]
* Add a svukte extension check in RV32.
* Refine the code.

[v3]
* Fix some typos
* Refine code by separating a function into two dedicated functions.
* Follow the riscv,isa order

[v2]
* Refactor the code

[v1]
* Add svukte extension


Fea.Wang (6):
  target/riscv: Add svukte extension capability variable
  target/riscv: Support senvcfg[UKTE] bit when svukte extension is
    enabled
  target/riscv: Support hstatus[HUKTE] bit when svukte extension is
    enabled
  target/riscv: Check memory access to meet svukte rule
  target/riscv: Expose svukte ISA extension
  target/riscv: Check svukte is not enabled in RV32

 target/riscv/cpu.c         |  2 ++
 target/riscv/cpu_bits.h    |  2 ++
 target/riscv/cpu_cfg.h     |  1 +
 target/riscv/cpu_helper.c  | 55 ++++++++++++++++++++++++++++++++++++++
 target/riscv/csr.c         |  7 +++++
 target/riscv/tcg/tcg-cpu.c |  5 ++++
 6 files changed, 72 insertions(+)