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Date: Thu, 5 Dec 2024 16:34:05 +0500 Message-Id: <20241205-b4-ctr_upstream_v3-v5-0-60b993aa567d@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Change-ID: 20241029-b4-ctr_upstream_v3-7ab764c68bf1 X-Mailer: b4 0.14.2 Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=rkanwal@rivosinc.com; helo=mail-wm1-x341.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series enables Control Transfer Records extension support on riscv platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and this series is based on v1.0_rc6 [0] CTR extension depends on both the implementation of S-mode and Sscsrind extension v1.0.0 [1]. CTR access ctrsource, ctrtartget and ctrdata CSRs using sscsrind extension. The series is based on Smcdeleg/Ssccfg counter delegation extension [2] patches [3]. CTR itself doesn't depend on counter delegation support. This rebase is basically to include the Smcsrind patches. Here is the link to a quick start guide [4] to setup and run a basic perf demo on Linux to use CTR Ext. Qemu patches can be found here: https://github.com/rajnesh-kanwal/qemu/tree/b4/ctr_upstream_v5 Opensbi patch can be found here: https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream_v2 Linux kernel patches can be found here: https://github.com/rajnesh-kanwal/linux/tree/b4/ctr_upstream_v2 [0]: https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc6 [1]: https://github.com/riscvarchive/riscv-indirect-csr-access/releases/tag/v1.0.0 [2]: https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0 [3]: https://lore.kernel.org/qemu-riscv/20241203-counter_delegation-v4-0-c12a89baed86@rivosinc.com/ [4]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine Signed-off-by: Rajnesh Kanwal --- Changelog: v5: Improvements based on Richard Henderson's feedback. - Fixed code gen logic to use gen_update_pc() instead of tcg_constant_tl(). - Some function renaming. - Rebased onto v4 of counter delegation series. v4: Improvements based on Richard Henderson's feedback. - Refactored CTR related code generation to move more code into translation side and avoid unnecessary code execution in generated code. - Added missing code in machine.c to migrate the new state. - https://lore.kernel.org/r/20241204-b4-ctr_upstream_v3-v4-0-d3ce6bef9432@rivosinc.com v3: Improvements based on Jason Chien and Frank Chang's feedback. - Created single set of MACROs for CTR CSRs in cpu_bit.h - Some fixes in riscv_ctr_add_entry. - Return zero for vs/sireg4-6 for CTR 0x200 to 0x2ff range. - Improved extension dependency check. - Fixed invalid ctrctl csr selection bug in riscv_ctr_freeze. - Added implied rules for Smctr and Ssctr. - Added missing SMSTATEEN0_CTR bit in mstateen0 and hstateen0 write ops. - Some more cosmetic changes. - https://lore.kernel.org/qemu-riscv/20241104-b4-ctr_upstream_v3-v3-0-32fd3c48205f@rivosinc.com/ v2: Lots of improvements based on Jason Chien's feedback including: - Added CTR recording for cm.jalt, cm.jt, cm.popret, cm.popretz. - Fixed and added more CTR extension enable checks. - Fixed CTR CSR predicate functions. - Fixed external trap xTE bit checks. - One fix in freeze function for VS-mode. - Lots of minor code improvements. - Added checks in sctrclr instruction helper. - https://lore.kernel.org/qemu-riscv/20240619152708.135991-1-rkanwal@rivosinc.com/ v1: - https://lore.kernel.org/qemu-riscv/20240529160950.132754-1-rkanwal@rivosinc.com/ --- Rajnesh Kanwal (7): target/riscv: Remove obsolete sfence.vm instruction target/riscv: Add Control Transfer Records CSR definitions. target/riscv: Add support for Control Transfer Records extension CSRs. target/riscv: Add support to record CTR entries. target/riscv: Add CTR sctrclr instruction. target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. target/riscv: machine: Add Control Transfer Record state description target/riscv/cpu.c | 26 ++- target/riscv/cpu.h | 13 ++ target/riscv/cpu_bits.h | 94 ++++++++ target/riscv/cpu_cfg.h | 2 + target/riscv/cpu_helper.c | 266 ++++++++++++++++++++++ target/riscv/csr.c | 294 ++++++++++++++++++++++++- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_privileged.c.inc | 18 +- target/riscv/insn_trans/trans_rvi.c.inc | 75 +++++++ target/riscv/insn_trans/trans_rvzce.c.inc | 21 ++ target/riscv/machine.c | 25 +++ target/riscv/op_helper.c | 48 ++++ target/riscv/tcg/tcg-cpu.c | 11 + target/riscv/translate.c | 46 ++++ 15 files changed, 935 insertions(+), 8 deletions(-) --- base-commit: 685c44c5d40b6796e4a88c0335f7ae01cb7a2121 change-id: 20241029-b4-ctr_upstream_v3-7ab764c68bf1