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[RFC,v5,0/1] target/riscv: rvv: Use wider accesses for unit stride load/store

Message ID 20241211143118.661268-1-craig.blackmore@embecosm.com (mailing list archive)
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Series target/riscv: rvv: Use wider accesses for unit stride load/store | expand

Message

Craig Blackmore Dec. 11, 2024, 2:31 p.m. UTC 
Changes since v4:
- Split into a seperate submission to simplify review
- Use load/store atomic functions as suggested by Richard Henderson
- Do 8, 4, 2 byte atomic ldst for sizes smaller than 16 bytes

This patch now uses the atomic ldst functions from
accel/tcg/ldst_atomicity.c.inc to ensure element size atomicity.  I was
not sure of the best way to make these functions accessible from the
riscv target, so any suggestions are very welcome.

Previous versions:
- v1: https://lore.kernel.org/all/20240717153040.11073-1-paolo.savini@embecosm.com/
- v2: https://lore.kernel.org/all/20241002135708.99146-1-paolo.savini@embecosm.com/
- v3: https://lore.kernel.org/all/20241014220153.196183-1-paolo.savini@embecosm.com/
- v4: https://lore.kernel.org/all/20241029194348.59574-1-paolo.savini@embecosm.com/

Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Weiwei Li <liwei1518@gmail.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Helene Chelin <helene.chelin@embecosm.com>
Cc: Nathan Egge <negge@google.com>
Cc: Max Chou <max.chou@sifive.com>

Craig Blackmore (1):
  target/riscv: rvv: Use wider accesses for unit stride load/store

 target/riscv/trace-events    | 12 +++++
 target/riscv/vector_helper.c | 95 +++++++++++++++++++++++++++++++++---
 2 files changed, 101 insertions(+), 6 deletions(-)