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[14.200.18.130]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72918af0caesm7900933b3a.86.2024.12.17.23.42.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Dec 2024 23:42:41 -0800 (PST) From: Nicholas Piggin To: qemu-devel@nongnu.org Cc: Nicholas Piggin , "Michael S . Tsirkin" , Marcel Apfelbaum , Dmitry Fleytman , Akihiko Odaki , Sriram Yagnaraman , Fabiano Rosas , Laurent Vivier , Paolo Bonzini Subject: [PATCH 0/5] qtest: pci and e1000e/igb msix fixes Date: Wed, 18 Dec 2024 17:42:26 +1000 Message-ID: <20241218074232.1784427-1-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=npiggin@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This series is split out from a larger one that added some more XHCI functionality and tests here. Just wanted to get more focus on the PCI issues first. https://lore.kernel.org/qemu-devel/20241212083502.1439033-1-npiggin@gmail.com/T/#t It is quite reworked after feedback about the incorrect PBA write implementation. This one solves the e1000e/igb multiple-intrrupt problem by enabling the msix vector which delivers the interrupt and lowers the PBA pending bit. I'm still curious about PCI spec note that masked pending interrupt must have PBA bit cleared if the interrupt condition in the function clears, which no device seems to implement... but at least for now, unmasking and delivering seems to be the reliable way to clear the interrupt. Thanks, Nick Nicholas Piggin (5): qtest/pci: Enforce balanced iomap/unmap qtest/libqos/pci: Fix qpci_msix_enable sharing bar0 qtest/libqos/pci: Do not write to PBA memory qtest/e1000e|igb: Clear interrupt-cause bits after irq qtest/e1000e|igb: Fix msix to re-trigger interrupts tests/qtest/libqos/ahci.h | 1 + tests/qtest/libqos/e1000e.h | 8 +++ tests/qtest/libqos/pci.h | 3 + tests/qtest/libqos/virtio-pci.h | 1 + tests/qtest/ahci-test.c | 2 + tests/qtest/e1000e-test.c | 10 ++- tests/qtest/igb-test.c | 10 ++- tests/qtest/libqos/ahci.c | 6 ++ tests/qtest/libqos/e1000e.c | 113 +++++++++++++++++++++++++++++++- tests/qtest/libqos/pci.c | 74 ++++++++++++++++++--- tests/qtest/libqos/virtio-pci.c | 6 +- 11 files changed, 217 insertions(+), 17 deletions(-)