[RFC,0/1] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

Message

Paolo Savini Dec. 18, 2024, 5:08 p.m. UTC

The following patch aims at speeding up the emulation of whole register loads/stores by generating tcg operations rather then going through the call of a helper function.
The proposed implementation aims at using atomic 16 byte loads and store when possible and it updates the value of vstart in order to keep the state of the cpu consistent.
This kind of precaution doesn't seem to be followed by other vector operations that use tcg ops generation so this might be redundant.
Also the atomicity requirements of qemu loads and stores get removed if we are running in serial mode (!CF_PARALLEL).
In light of this I wonder whether exceptions could be a concern or not in the context of tcg ops generation, above all when it comes to updating the state of the cpu consistently (vstart).
Any feedback welcome.

The proposed implementation aims at replacing the correspondent helper function, that will be removed in the final version of the patch, unless there are corner cases where it is still necessary to use it. 

Cc: Richard Handerson <[e-mail]>
Cc: Palmer Dabbelt <[e-mail]>
Cc: Alistair Francis <[e-mail]>
Cc: Bin Meng <[e-mail]>
Cc: Weiwei Li <[e-mail]>
Cc: Daniel Henrique Barboza <[e-mail]>
Cc: Liu Zhiwei <[e-mail]>
Cc: Helene Chelin <[e-mail]>
Cc: Nathan Egge <[e-mail]>
Cc: Max Chou <[e-mail]>
Cc: Jeremy Bennett <[e-mail]>
Cc: Craig Blackmore <[e-mail]>

Paolo Savini (1):
  target/riscv: use tcg ops generation to emulate whole reg rvv
    loads/stores.

 target/riscv/insn_trans/trans_rvv.c.inc | 104 +++++++++++++-----------
 1 file changed, 56 insertions(+), 48 deletions(-)