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[109.118.46.116]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aabfbbb7a52sm70403966b.58.2024.12.18.09.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 09:08:44 -0800 (PST) From: Paolo Savini To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Paolo Savini , Richard Handerson , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Helene Chelin , Nathan Egge , Max Chou , Jeremy Bennett , Craig Blackmore Subject: [RFC 0/1] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores. Date: Wed, 18 Dec 2024 17:08:39 +0000 Message-ID: <20241218170840.1090473-1-paolo.savini@embecosm.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=paolo.savini@embecosm.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The following patch aims at speeding up the emulation of whole register loads/stores by generating tcg operations rather then going through the call of a helper function. The proposed implementation aims at using atomic 16 byte loads and store when possible and it updates the value of vstart in order to keep the state of the cpu consistent. This kind of precaution doesn't seem to be followed by other vector operations that use tcg ops generation so this might be redundant. Also the atomicity requirements of qemu loads and stores get removed if we are running in serial mode (!CF_PARALLEL). In light of this I wonder whether exceptions could be a concern or not in the context of tcg ops generation, above all when it comes to updating the state of the cpu consistently (vstart). Any feedback welcome. The proposed implementation aims at replacing the correspondent helper function, that will be removed in the final version of the patch, unless there are corner cases where it is still necessary to use it. Cc: Richard Handerson Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Bin Meng Cc: Weiwei Li Cc: Daniel Henrique Barboza Cc: Liu Zhiwei Cc: Helene Chelin Cc: Nathan Egge Cc: Max Chou Cc: Jeremy Bennett Cc: Craig Blackmore Paolo Savini (1): target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores. target/riscv/insn_trans/trans_rvv.c.inc | 104 +++++++++++++----------- 1 file changed, 56 insertions(+), 48 deletions(-)