[RFC,0/1] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

Message

Paolo Savini Dec. 20, 2024, 3:34 p.m. UTC

Following the reviews on the previous version:

- RFC v1: https://lore.kernel.org/all/[e-mail]/
- Review: https://lore.kernel.org/all/[e-mail]/

we apply the following fixes:

- Fall back to using the helper function if vstart != 0 at the beginning
  of the iterations and refactor the setting of the function arguments
  accordignly.
- Add mark_vs_dirty before performing the memory operations.
- Loosen the atomicity constraints and apply only MO_ATOM_IFALIGN_PAIR
  for element sizes MO_16, MO_32 and MO_64.
- Change the way we update vstart in order to set vstart to 0 if it's the last
  iteration.
- Fix the indentation.

We also rephrase the commit message to better reflect the new behaviour of the
patch.

Many thanks Richard for the thorough review and explanations.

Cc: Richard Handerson <[e-mail]>
Cc: Palmer Dabbelt <[e-mail]>
Cc: Alistair Francis <[e-mail]>
Cc: Bin Meng <[e-mail]>
Cc: Weiwei Li <[e-mail]>
Cc: Daniel Henrique Barboza <[e-mail]>
Cc: Liu Zhiwei <[e-mail]>
Cc: Helene Chelin <[e-mail]>
Cc: Nathan Egge <[e-mail]>
Cc: Max Chou <[e-mail]>
Cc: Jeremy Bennett <[e-mail]>
Cc: Craig Blackmore <[e-mail]>


Paolo Savini (1):
  target/riscv: use tcg ops generation to emulate whole reg rvv
    loads/stores.

 target/riscv/insn_trans/trans_rvv.c.inc | 125 +++++++++++++++---------
 1 file changed, 78 insertions(+), 47 deletions(-)