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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a8e37d154sm20636654f8f.10.2025.01.16.03.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jan 2025 03:25:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 0/2] target/i386: Fix 0 * Inf + QNaN regression Date: Thu, 16 Jan 2025 11:25:34 +0000 Message-Id: <20250116112536.4117889-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patchset fixes a regression that I introduced in my recent refactoring of softfloat NaN handling, in commit 8adcff4ae7 ("fpu: handle raising Invalid for infzero in pick_nan_muladd"). When I wrote that code I was under the impression that all architectures would raise Invalid for the "inf * zero + NaN" case of a fused multiply-add. However, IEEE 754-2008 makes this impdef for QNaN: an architecture can choose whether to raise Invalid or not. For i386, SDM section 14.5.2 documents that for the 0 * Inf + NaN case that it will only raise the Invalid exception when the input is a signalling NaN, and so the behaviour change in 8adcff4ae7 that caused it to raise Invalid also for the QNaN case is wrong. The first commit here adds a knob to the softfloat code to allow an architecture to disable the "raise Invalid" that is the default, and makes x86 set that. The second commit is a test case for x86 check-tcg that exercises this corner case. We do not revert here the behaviour change for hppa, sh4 or tricore: * The sh4 manual is clear that it should signal Invalid * The tricore manual is a bit vague but doesn't say it shouldn't * The hppa manual doesn't talk about fused multiply-add corner cases at all The test case also includes a disabled test for a different x86 fma corner case; this is one that's not a regression. I've left it in the test case code because it's the justification for why the test harness has the support for testing fma insns with FTZ set. I'm working on a fix for that but I don't think it should be tangled up with fixing this regression. thanks -- PMM Peter Maydell (2): target/i386: Do not raise Invalid for 0 * Inf + QNaN tests/tcg/x86_64/fma: Test some x86 fused-multiply-add cases include/fpu/softfloat-types.h | 16 ++++- target/i386/tcg/fpu_helper.c | 5 +- tests/tcg/x86_64/fma.c | 109 +++++++++++++++++++++++++++++++ fpu/softfloat-parts.c.inc | 5 +- tests/tcg/x86_64/Makefile.target | 1 + 5 files changed, 130 insertions(+), 6 deletions(-) create mode 100644 tests/tcg/x86_64/fma.c