[v10,0/8] Support RISC-V IOPMP

Message

Ethan Chen Jan. 22, 2025, 8:36 a.m. UTC

When IOPMP is enabled, memory access to system memory from devices and
the CPU will be checked by the IOPMP.

The issue of CPU access to non-CPU address space via IOMMU was previously
mentioned by Jim Shu, who provided a patch[1] to fix it. IOPMP also requires
this patch.

You can use a customized QEMU[2] to run bare-metal demo[3] to show IOPMP
functionality. The modifications involve applying patch[1] and adding a simple
DMA device along with a second IOPMP device to the virt machine. These
additional devices are intended to demonstrate more complex scenarios for IOPMP.

[1] accel/tcg: Store section pointer in CPUTLBEntryFull
    https://patchew.org/QEMU/[e-mail]/[e-mail]/
[2] https://github.com/zhanyangch/qemu/tree/iopmp_patch_test
[3] https://github.com/zhanyangch/iopmp-test

Changes for v10:

  - Fix a build error for iopmp_dispatcher
  - The mmio size of IOPMP device is calculated based on properties, rather
    than relying on a fixed value

Changes for v9:

  - Change the specification version to v0.9.2 RC3
  - Remove API for configuration CPU IOPMP property (Alistair)
  - Add a dispatcher device to forward iopmp transaction information

Changes for v8:

  - Support transactions from CPU
  - Add an API to set up IOPMP protection for system memory
  - Add an API to configure the RISCV CPU to support IOPMP and specify the
    CPU's RRID
  - Add an API for DMA operation with IOPMP support
  - Add SPDX license identifiers to new files (Stefan W.)
  - Remove IOPMP PCI interface(pci_setup_iommu) (Zhiwei)

Changes for v7:

  - Change the specification version to v0.9.1
  - Remove the sps extension
  - Remove stall support, transaction information which need requestor device
    support.
  - Remove iopmp_cascade option for virt machine
  - Refine 'addr' range checks switch case (Daniel)

Ethan Chen (8):
  hw/core: Add config stream
  memory: Introduce memory region fetch operation
  system/physmem: Support IOMMU granularity smaller than TARGET_PAGE
    size
  target/riscv: Add support for IOPMP
  hw/misc/riscv_iopmp_txn_info: Add struct for transaction infomation
  hw/misc/riscv_iopmp: Add RISC-V IOPMP device
  hw/misc/riscv_iopmp_dispatcher: Device for redirect IOPMP transaction
    infomation
  hw/riscv/virt: Add IOPMP support

 accel/tcg/cputlb.c                       |   29 +-
 docs/system/riscv/virt.rst               |    7 +
 hw/Kconfig                               |    1 +
 hw/core/Kconfig                          |    3 +
 hw/core/meson.build                      |    2 +-
 hw/misc/Kconfig                          |    4 +
 hw/misc/meson.build                      |    2 +
 hw/misc/riscv_iopmp.c                    | 2182 ++++++++++++++++++++++
 hw/misc/riscv_iopmp_dispatcher.c         |  136 ++
 hw/misc/trace-events                     |    4 +
 hw/riscv/Kconfig                         |    1 +
 hw/riscv/virt.c                          |   75 +
 include/exec/memory.h                    |   27 +
 include/hw/misc/riscv_iopmp.h            |  191 ++
 include/hw/misc/riscv_iopmp_dispatcher.h |   61 +
 include/hw/misc/riscv_iopmp_txn_info.h   |   38 +
 include/hw/riscv/virt.h                  |    4 +
 system/memory.c                          |  104 ++
 system/physmem.c                         |    4 +
 system/trace-events                      |    2 +
 target/riscv/cpu.c                       |    3 +
 target/riscv/cpu_cfg.h                   |    2 +
 target/riscv/cpu_helper.c                |   18 +-
 23 files changed, 2890 insertions(+), 10 deletions(-)
 create mode 100644 hw/misc/riscv_iopmp.c
 create mode 100644 hw/misc/riscv_iopmp_dispatcher.c
 create mode 100644 include/hw/misc/riscv_iopmp.h
 create mode 100644 include/hw/misc/riscv_iopmp_dispatcher.h
 create mode 100644 include/hw/misc/riscv_iopmp_txn_info.h